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Feature #3446 » bge_nexenta_fixes-020814.patch

Anonymous, 2014-02-08 05:56 PM

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usr/src/uts/common/io/bge/bge_hw.h 2014-02-08 12:19:12.277392300 -0500
23 23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24
 */
25 25

  
26
/*
27
 * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
28
 */
29

  
26 30
#ifndef _BGE_HW_H
27 31
#define	_BGE_HW_H
28 32

  
......
68 72
#define	DEVICE_ID_5724			0x165c
69 73
#define	DEVICE_ID_5705M			0x165d
70 74
#define	DEVICE_ID_5705MA3		0x165e
75
#define	DEVICE_ID_5719			0x1657
76
#define	DEVICE_ID_5720			0x165f
71 77
#define	DEVICE_ID_5705F			0x166e
72 78
#define	DEVICE_ID_5780			0x166a
73 79
#define	DEVICE_ID_5782			0x1696
80
#define	DEVICE_ID_5784M			0x1698
74 81
#define	DEVICE_ID_5785			0x1699
75 82
#define	DEVICE_ID_5787			0x169b
76 83
#define	DEVICE_ID_5787M			0x1693
......
92 99
#define	DEVICE_ID_5714S			0x1669
93 100
#define	DEVICE_ID_5715C			0x1678
94 101
#define	DEVICE_ID_5715S			0x1679
95
#define	DEVICE_ID_5761E			0x1680
96 102
#define	DEVICE_ID_5761			0x1681
103
#define	DEVICE_ID_5761E			0x1680
104
#define	DEVICE_ID_5761S			0x1688
105
#define	DEVICE_ID_5761SE		0x1689
97 106
#define	DEVICE_ID_5764			0x1684
98 107
#define	DEVICE_ID_5906			0x1712
99 108
#define	DEVICE_ID_5906M			0x1713
109
#define	DEVICE_ID_57760			0x1690
100 110
#define	DEVICE_ID_57780			0x1692
111
#define	DEVICE_ID_57788			0x1691
112
#define	DEVICE_ID_57790			0x1694
113
#define	DEVICE_ID_57781			0x16b1
114
#define	DEVICE_ID_57785			0x16b5
115
#define	DEVICE_ID_57761			0x16b0
116
#define	DEVICE_ID_57765			0x16b4
117
#define	DEVICE_ID_57791			0x16b2
118
#define	DEVICE_ID_57795			0x16b6
119
#define	DEVICE_ID_57762			0x1682
120
#define	DEVICE_ID_57766			0x1686
121
#define	DEVICE_ID_57786			0x16b3
122
#define	DEVICE_ID_57782			0x16b7
101 123

  
102 124
#define	REVISION_ID_5700_B0		0x10
103 125
#define	REVISION_ID_5700_B2		0x12
......
189 211
#define	DEVICE_5717_SERIES_CHIPSETS(bgep) \
190 212
		(bgep->chipid.device == DEVICE_ID_5717) ||\
191 213
		(bgep->chipid.device == DEVICE_ID_5718) ||\
214
		(bgep->chipid.device == DEVICE_ID_5719) ||\
215
		(bgep->chipid.device == DEVICE_ID_5720) ||\
192 216
		(bgep->chipid.device == DEVICE_ID_5724)
193 217

  
194 218
#define	DEVICE_5723_SERIES_CHIPSETS(bgep) \
195 219
		((bgep->chipid.device == DEVICE_ID_5723) ||\
196 220
		(bgep->chipid.device == DEVICE_ID_5761) ||\
197 221
		(bgep->chipid.device == DEVICE_ID_5761E) ||\
222
		(bgep->chipid.device == DEVICE_ID_5761S) ||\
223
		(bgep->chipid.device == DEVICE_ID_5761SE) ||\
198 224
		(bgep->chipid.device == DEVICE_ID_5764) ||\
225
		(bgep->chipid.device == DEVICE_ID_5784M) ||\
199 226
		(bgep->chipid.device == DEVICE_ID_5785) ||\
200
		(bgep->chipid.device == DEVICE_ID_57780))
227
		(bgep->chipid.device == DEVICE_ID_57760) ||\
228
		(bgep->chipid.device == DEVICE_ID_57780) ||\
229
		(bgep->chipid.device == DEVICE_ID_57788) ||\
230
		(bgep->chipid.device == DEVICE_ID_57790))
201 231

  
202 232
#define	DEVICE_5714_SERIES_CHIPSETS(bgep) \
203 233
		((bgep->chipid.device == DEVICE_ID_5714C) ||\
......
209 239
		((bgep->chipid.device == DEVICE_ID_5906) ||\
210 240
		(bgep->chipid.device == DEVICE_ID_5906M))
211 241

  
242

  
243
#define	CHIP_TYPE_5705_PLUS   (1 << 0)
244
#define	CHIP_TYPE_5750_PLUS   (1 << 1)
245
#define	CHIP_TYPE_5780_CLASS  (1 << 2)
246
#define	CHIP_TYPE_5755_PLUS   (1 << 3)
247
#define	CHIP_TYPE_57765_CLASS (1 << 4)
248
#define	CHIP_TYPE_57765_PLUS  (1 << 5)
249
#define	CHIP_TYPE_5717_PLUS   (1 << 6)
250

  
251
#define	DEVICE_IS_57765_PLUS(bgep) \
252
	(bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
253
#define	DEVICE_IS_5755_PLUS(bgep) \
254
	(bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)
255

  
212 256
/*
213 257
 * Second section:
214 258
 *	Offsets of important registers & definitions for bits therein
......
225 269
 */
226 270
#define	PCI_CONF_BGE_MHCR		0x68
227 271
#define	MHCR_CHIP_REV_MASK		0xffff0000
272
#define	MHCR_CHIP_REV_SHIFT		16
228 273
#define	MHCR_ENABLE_TAGGED_STATUS_MODE	0x00000200
229 274
#define	MHCR_MASK_INTERRUPT_MODE	0x00000100
230 275
#define	MHCR_ENABLE_INDIRECT_ACCESS	0x00000080
......
236 281
#define	MHCR_MASK_PCI_INT_OUTPUT	0x00000002
237 282
#define	MHCR_CLEAR_INTERRUPT_INTA	0x00000001
238 283

  
239
#define	MHCR_CHIP_REV_5700_B0		0x71000000
240
#define	MHCR_CHIP_REV_5700_B2		0x71020000
241
#define	MHCR_CHIP_REV_5700_B3		0x71030000
242
#define	MHCR_CHIP_REV_5700_C0		0x72000000
243
#define	MHCR_CHIP_REV_5700_C1		0x72010000
244
#define	MHCR_CHIP_REV_5700_C2		0x72020000
245

  
246
#define	MHCR_CHIP_REV_5701_A0		0x00000000
247
#define	MHCR_CHIP_REV_5701_A2		0x00020000
248
#define	MHCR_CHIP_REV_5701_A3		0x00030000
249
#define	MHCR_CHIP_REV_5701_A5		0x01050000
250

  
251
#define	MHCR_CHIP_REV_5702_A0		0x10000000
252
#define	MHCR_CHIP_REV_5702_A1		0x10010000
253
#define	MHCR_CHIP_REV_5702_A2		0x10020000
254

  
255
#define	MHCR_CHIP_REV_5703_A0		0x10000000
256
#define	MHCR_CHIP_REV_5703_A1		0x10010000
257
#define	MHCR_CHIP_REV_5703_A2		0x10020000
258
#define	MHCR_CHIP_REV_5703_B0		0x11000000
259
#define	MHCR_CHIP_REV_5703_B1		0x11010000
260

  
261
#define	MHCR_CHIP_REV_5704_A0		0x20000000
262
#define	MHCR_CHIP_REV_5704_A1		0x20010000
263
#define	MHCR_CHIP_REV_5704_A2		0x20020000
264
#define	MHCR_CHIP_REV_5704_A3		0x20030000
265
#define	MHCR_CHIP_REV_5704_B0		0x21000000
266

  
267
#define	MHCR_CHIP_REV_5705_A0		0x30000000
268
#define	MHCR_CHIP_REV_5705_A1		0x30010000
269
#define	MHCR_CHIP_REV_5705_A2		0x30020000
270
#define	MHCR_CHIP_REV_5705_A3		0x30030000
271
#define	MHCR_CHIP_REV_5705_A5		0x30050000
272

  
273
#define	MHCR_CHIP_REV_5782_A0		0x30030000
274
#define	MHCR_CHIP_REV_5782_A1		0x30030088
275

  
276
#define	MHCR_CHIP_REV_5788_A1		0x30050000
277

  
278
#define	MHCR_CHIP_REV_5751_A0		0x40000000
279
#define	MHCR_CHIP_REV_5751_A1		0x40010000
280

  
281
#define	MHCR_CHIP_REV_5721_A0		0x41000000
282
#define	MHCR_CHIP_REV_5721_A1		0x41010000
283

  
284
#define	MHCR_CHIP_REV_5714_A0		0x50000000
285
#define	MHCR_CHIP_REV_5714_A1		0x90010000
286

  
287
#define	MHCR_CHIP_REV_5715_A0		0x50000000
288
#define	MHCR_CHIP_REV_5715_A1		0x90010000
289

  
290
#define	MHCR_CHIP_REV_5715S_A0		0x50000000
291
#define	MHCR_CHIP_REV_5715S_A1		0x90010000
292

  
293
#define	MHCR_CHIP_REV_5754_A0		0xb0000000
294
#define	MHCR_CHIP_REV_5754_A1		0xb0010000
295

  
296
#define	MHCR_CHIP_REV_5787_A0		0xb0000000
297
#define	MHCR_CHIP_REV_5787_A1		0xb0010000
298
#define	MHCR_CHIP_REV_5787_A2		0xb0020000
299

  
300
#define	MHCR_CHIP_REV_5755_A0		0xa0000000
301
#define	MHCR_CHIP_REV_5755_A1		0xa0010000
302

  
303
#define	MHCR_CHIP_REV_5906_A0		0xc0000000
304
#define	MHCR_CHIP_REV_5906_A1		0xc0010000
305
#define	MHCR_CHIP_REV_5906_A2		0xc0020000
306

  
307
#define	MHCR_CHIP_REV_5723_A0		0xf0000000
308
#define	MHCR_CHIP_REV_5723_A1		0xf0010000
309
#define	MHCR_CHIP_REV_5723_A2		0xf0020000
310
#define	MHCR_CHIP_REV_5723_B0		0xf1000000
311

  
312
#define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) & 0xf0000000)
313
#define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
314
#define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
315
#define	MHCR_CHIP_ASIC_REV_5703		(0x1 << 28)
316
#define	MHCR_CHIP_ASIC_REV_5704		(0x2 << 28)
317
#define	MHCR_CHIP_ASIC_REV_5705		(0x3 << 28)
318
#define	MHCR_CHIP_ASIC_REV_5721_5751	(0x4 << 28)
319
#define	MHCR_CHIP_ASIC_REV_5714 	(0x5 << 28)
320
#define	MHCR_CHIP_ASIC_REV_5752		(0x6 << 28)
321
#define	MHCR_CHIP_ASIC_REV_5754		(0xb << 28)
322
#define	MHCR_CHIP_ASIC_REV_5787		((uint32_t)0xb << 28)
323
#define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
324
#define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
325
#define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
326
#define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
327

  
284
#define	MHCR_CHIP_REV_5703_A0		0x1000
285
#define	MHCR_CHIP_REV_5704_A0		0x2000
286
#define	MHCR_CHIP_REV_5751_A0		0x4000
287
#define	MHCR_CHIP_REV_5721_A0		0x4100
288
#define	MHCR_CHIP_REV_5755_A0		0xa000
289
#define	MHCR_CHIP_REV_5755_A1		0xa001
290
#define	MHCR_CHIP_REV_5719_A0		0x05719000
291
#define	MHCR_CHIP_REV_5720_A0		0x05720000
292

  
293
#define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) >> 12)
294
#define	MHCR_CHIP_ASIC_REV_5700		0x07
295
#define	MHCR_CHIP_ASIC_REV_5701		0x00
296
#define	MHCR_CHIP_ASIC_REV_5703		0x01
297
#define	MHCR_CHIP_ASIC_REV_5704		0x02
298
#define	MHCR_CHIP_ASIC_REV_5705		0x03
299
#define	MHCR_CHIP_ASIC_REV_5750		0x04
300
#define	MHCR_CHIP_ASIC_REV_5752		0x06
301
#define	MHCR_CHIP_ASIC_REV_5780		0x08
302
#define	MHCR_CHIP_ASIC_REV_5714		0x09
303
#define	MHCR_CHIP_ASIC_REV_5755		0x0a
304
#define	MHCR_CHIP_ASIC_REV_5787		0x0b
305
#define	MHCR_CHIP_ASIC_REV_5906		0x0c
306
#define	MHCR_CHIP_ASIC_REV_PRODID	0x0f
307
#define	MHCR_CHIP_ASIC_REV_5784		0x5784
308
#define	MHCR_CHIP_ASIC_REV_5761		0x5761
309
#define	MHCR_CHIP_ASIC_REV_5785		0x5785
310
#define	MHCR_CHIP_ASIC_REV_5717		0x5717
311
#define	MHCR_CHIP_ASIC_REV_5719		0x5719
312
#define	MHCR_CHIP_ASIC_REV_5720		0x5720
313
#define	MHCR_CHIP_ASIC_REV_57780	0x57780
314
#define	MHCR_CHIP_ASIC_REV_57765	0x57785
315
#define	MHCR_CHIP_ASIC_REV_57766	0x57766
328 316

  
329 317
/*
330 318
 * PCI DMA read/write Control Register, in PCI config space
......
466 454
#define	PCI_CONF_DEV_STUS_5723		0xd6
467 455
#define	DEVICE_ERROR_STUS		0xf
468 456

  
457
#define	PCI_CONF_PRODID_ASICREV		0x000000bc
458
#define	PCI_CONF_GEN2_PRODID_ASICREV	0x000000f4
459
#define	PCI_CONF_GEN15_PRODID_ASICREV	0x000000fc
460

  
469 461
#define	NIC_MEM_WINDOW_OFFSET		0x00008000	/* 32k	*/
470 462

  
471 463
/*
......
541 533
#define	MEMORY_ARBITER_MODE_REG		0x4000
542 534
#define	BUFFER_MANAGER_MODE_REG		0x4400
543 535
#define	READ_DMA_MODE_REG		0x4800
536
#define	READ_DMA_RESERVED_CONTROL_REG	0x4900
544 537
#define	WRITE_DMA_MODE_REG		0x4c00
545 538
#define	DMA_COMPLETION_MODE_REG		0x6400
546 539

  
......
552 545
 * Transmit MAC Mode Register
553 546
 * (TRANSMIT_MAC_MODE_REG, 0x045c)
554 547
 */
548
#define	TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
549
#define	TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
550
#define	TRANSMIT_MODE_MBUF_LOCKUP_FIX	0x00000100
555 551
#define	TRANSMIT_MODE_LONG_PAUSE	0x00000040
556 552
#define	TRANSMIT_MODE_BIG_BACKOFF	0x00000020
557 553
#define	TRANSMIT_MODE_FLOW_CONTROL	0x00000010
......
619 615
 */
620 616
#define	BUFF_MGR_TEST_MODE		0x00000008
621 617
#define	BUFF_MGR_MBUF_LOW_ATTN_ENABLE	0x00000010
618
#define	BUFF_MGR_NO_TX_UNDERRUN		0x80000000
622 619

  
623 620
#define	BUFF_MGR_ALL_ATTN_BITS		0x00000014
624 621

  
625 622
/*
626 623
 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
627
 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
624
 * 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
625
 * WRITE_DMA_MODE_REG, 0x4c00)
628 626
 *
629 627
 * These registers each contain a 2-bit priority field, which controls
630 628
 * the relative priority of that type of DMA (read vs. write vs. MSI),
......
635 633
#define	DMA_PRIORITY_SHIFT		30
636 634
#define	ALL_DMA_ATTN_BITS		0x000003fc
637 635

  
636
#define	RDMA_RSRVCTRL_FIFO_OFLW_FIX	 0x00000004
637
#define	RDMA_RSRVCTRL_FIFO_LWM_1_5K	 0x00000c00
638
#define	RDMA_RSRVCTRL_FIFO_LWM_MASK	 0x00000ff0
639
#define	RDMA_RSRVCTRL_FIFO_HWM_1_5K	 0x000c0000
640
#define	RDMA_RSRVCTRL_FIFO_HWM_MASK	 0x000ff000
641
#define	RDMA_RSRVCTRL_TXMRGN_320B	 0x28000000
642
#define	RDMA_RSRVCTRL_TXMRGN_MASK	 0xffe00000
643

  
644

  
638 645
/*
639 646
 * BCM5755, 5755M, 5906, 5906M only
640 647
 * 1 - Enable Fix. Device will send out the status block before
......
644 651
 */
645 652
#define	DMA_STATUS_TAG_FIX_CQ12384	0x20000000
646 653

  
654
/* 5720 only */
655
#define	DMA_H2BNC_VLAN_DET		0x20000000
656

  
657

  
647 658
/*
648 659
 * End of state machine control register definitions
649 660
 */
......
781 792
#define	MAC_RX_MTU_DEFAULT		0x000005f2	/* 1522	*/
782 793
#define	MAC_TX_LENGTHS_REG		0x0464
783 794
#define	MAC_TX_LENGTHS_DEFAULT		0x00002620
795
#define	MAC_TX_LENGTHS_JMB_FRM_LEN_MSK	 0x00ff0000
796
#define	MAC_TX_LENGTHS_CNT_DWN_VAL_MSK	 0xff000000
784 797

  
785 798
/*
786 799
 * MII access registers
......
1069 1082
#define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
1070 1083

  
1071 1084
/*
1072
 * CPMU registers (5717/5718 only)
1085
 * CPMU registers (5717/5718/5719/5720 only)
1073 1086
 */
1074
#define	CPMU_STATUS_REG	0x362c
1075
#define	CPMU_STATUS_FUN_NUM	0x20000000
1087
#define	CPMU_CLCK_ORIDE_REG		0x3624
1088
#define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
1089

  
1090
#define	CPMU_STATUS_REG			0x362c
1091
#define	CPMU_STATUS_FUN_NUM_5717	0x20000000
1092
#define	CPMU_STATUS_FUN_NUM_5719	0xc0000000
1093
#define	CPMU_STATUS_FUN_NUM_5719_SHIFT	30
1094

  
1076 1095

  
1077 1096
/*
1078 1097
 * Host Coalescing Engine Control Registers
......
1191 1210
#define	VCPU_EXT_CTL			0x6890
1192 1211
#define	VCPU_EXT_CTL_HALF		0x00400000
1193 1212

  
1213
#define	GRC_FASTBOOT_PC			0x6894
1214

  
1194 1215
#define	FTQ_RESET_REG			0x5c00
1195 1216

  
1196 1217
#define	MSI_MODE_REG			0x6000
......
1210 1231
#define	MODE_INT_ON_TXRISC_ATTN		0x01000000
1211 1232
#define	MODE_RECV_NO_PSEUDO_HDR_CSUM	0x00800000
1212 1233
#define	MODE_SEND_NO_PSEUDO_HDR_CSUM	0x00100000
1234
#define	MODE_HTX2B_ENABLE		0x00040000
1213 1235
#define	MODE_HOST_SEND_BDS		0x00020000
1214 1236
#define	MODE_HOST_STACK_UP		0x00010000
1215 1237
#define	MODE_FORCE_32_BIT_PCI		0x00008000
1238
#define	MODE_B2HRX_ENABLE		0x00008000
1216 1239
#define	MODE_NO_INT_ON_RECV		0x00004000
1217 1240
#define	MODE_NO_INT_ON_SEND		0x00002000
1218 1241
#define	MODE_ALLOW_BAD_FRAMES		0x00000800
1219 1242
#define	MODE_NO_CRC			0x00000400
1220 1243
#define	MODE_NO_FRAME_CRACKING		0x00000200
1244
#define	MODE_WORD_SWAP_B2HRX_DATA	0x00000080
1245
#define	MODE_BYTE_SWAP_B2HRX_DATA	0x00000040
1221 1246
#define	MODE_WORD_SWAP_FRAME		0x00000020
1222 1247
#define	MODE_BYTE_SWAP_FRAME		0x00000010
1223 1248
#define	MODE_WORD_SWAP_NONFRAME		0x00000004
......
1246 1271
 */
1247 1272
#define	CORE_CLOCK_MHZ			66
1248 1273
#define	MISC_CONFIG_REG			0x6804
1249
#define	MISC_CONFIG_GRC_RESET_DISABLE   0x20000000
1274
#define	MISC_CONFIG_GRC_RESET_DISABLE	0x20000000
1250 1275
#define	MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
1251 1276
#define	MISC_CONFIG_POWERDOWN		0x00100000
1252 1277
#define	MISC_CONFIG_POWER_STATE		0x00060000
......
1567 1592
#define	BGE_MINI_SLOTS_MAX		1024
1568 1593
#define	BGE_RECV_SLOTS_MAX		2048
1569 1594
#define	BGE_RECV_SLOTS_5705		512
1595
#define	BGE_RECV_SLOTS_5717		1024
1570 1596
#define	BGE_RECV_SLOTS_5782		512
1571 1597
#define	BGE_RECV_SLOTS_5721		512
1572 1598

  
......
2100 2126
#endif
2101 2127

  
2102 2128
#endif	/* _BGE_HW_H */
2129

  
2130

  
2103
-- usr/src/uts/common/io/bge/bge_chip2.c	2014-02-06 19:04:47.000000000 -0500
2131
++ usr/src/uts/common/io/bge/bge_chip2.c	2014-02-08 12:19:12.208055200 -0500
......
24 24
 */
25 25

  
26 26
/*
27
 * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
27
 * Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
28 28
 */
29 29

  
30 30
#include "bge_impl.h"
......
363 363
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
364 364
		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
365 365
	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
366
	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
366
	cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK) >> MHCR_CHIP_REV_SHIFT;
367
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_PRODID) {
368
		uint32_t reg;
369
		switch (cidp->device) {
370
		case DEVICE_ID_5717:
371
		case DEVICE_ID_5718:
372
		case DEVICE_ID_5719:
373
		case DEVICE_ID_5720:
374
			reg = PCI_CONF_GEN2_PRODID_ASICREV;
375
			break;
376
		case DEVICE_ID_57781:
377
		case DEVICE_ID_57785:
378
		case DEVICE_ID_57761:
379
		case DEVICE_ID_57765:
380
		case DEVICE_ID_57791:
381
		case DEVICE_ID_57795:
382
		case DEVICE_ID_57762:
383
		case DEVICE_ID_57766:
384
		case DEVICE_ID_57782:
385
		case DEVICE_ID_57786:
386
			reg = PCI_CONF_GEN15_PRODID_ASICREV;
387
			break;
388
		default:
389
			reg = PCI_CONF_PRODID_ASICREV;
390
			break;
391
		}
392
		cidp->asic_rev = pci_config_get32(handle, reg);
393
	}
367 394
	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
368 395
	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
369 396

  
......
386 413
	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
387 414
	    cidp->clsize, cidp->latency, cidp->command));
388 415

  
416
	cidp->chip_type = 0;
417
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5717 ||
418
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5719 ||
419
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5720)
420
		cidp->chip_type |= CHIP_TYPE_5717_PLUS;
421

  
422
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57765 ||
423
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57766)
424
		cidp->chip_type |= CHIP_TYPE_57765_CLASS;
425

  
426
	if (cidp->chip_type & CHIP_TYPE_57765_CLASS ||
427
	    cidp->chip_type & CHIP_TYPE_5717_PLUS)
428
		cidp->chip_type |= CHIP_TYPE_57765_PLUS;
429

  
430
	/* Intentionally exclude ASIC_REV_5906 */
431
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5755 ||
432
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5787 ||
433
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5784 ||
434
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5761 ||
435
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5785 ||
436
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57780 ||
437
	    cidp->chip_type & CHIP_TYPE_57765_PLUS)
438
		cidp->chip_type |= CHIP_TYPE_5755_PLUS;
439

  
440
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5780 ||
441
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5714)
442
		cidp->chip_type |= CHIP_TYPE_5780_CLASS;
443

  
444
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5750 ||
445
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5752 ||
446
	    MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5906 ||
447
	    cidp->chip_type & CHIP_TYPE_5755_PLUS ||
448
	    cidp->chip_type & CHIP_TYPE_5780_CLASS)
449
		cidp->chip_type |= CHIP_TYPE_5750_PLUS;
450

  
451
	if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5705 ||
452
	    cidp->chip_type & CHIP_TYPE_5750_PLUS)
453
		cidp->chip_type |= CHIP_TYPE_5705_PLUS;
454

  
389 455
	/*
390 456
	 * Step 2 (also step 6): disable and clear interrupts.
391 457
	 * Steps 11-13: configure PIO endianness options, and enable
......
445 511
	 * see whether the host is truly up to date, and regenerate
446 512
	 * its interrupt if not.
447 513
	 */
448
	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
514
	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
449 515
	    MHCR_ENABLE_TAGGED_STATUS_MODE |
516
	    MHCR_ENABLE_PCI_STATE_WRITE |
450 517
	    MHCR_MASK_INTERRUPT_MODE |
451 518
	    MHCR_CLEAR_INTERRUPT_INTA;
452 519

  
......
1896 1963
	case DEVICE_ID_5705_2:
1897 1964
	case DEVICE_ID_5717:
1898 1965
	case DEVICE_ID_5718:
1966
	case DEVICE_ID_5719:
1967
	case DEVICE_ID_5720:
1899 1968
	case DEVICE_ID_5724:
1969
	case DEVICE_ID_57760:
1900 1970
	case DEVICE_ID_57780:
1971
	case DEVICE_ID_57788:
1972
	case DEVICE_ID_57790:
1901 1973
	case DEVICE_ID_5780:
1902 1974
	case DEVICE_ID_5782:
1975
	case DEVICE_ID_5784M:
1903 1976
	case DEVICE_ID_5785:
1904 1977
	case DEVICE_ID_5787:
1905 1978
	case DEVICE_ID_5787M:
......
1918 1991
	case DEVICE_ID_5723:
1919 1992
	case DEVICE_ID_5761:
1920 1993
	case DEVICE_ID_5761E:
1994
	case DEVICE_ID_5761S:
1995
	case DEVICE_ID_5761SE:
1921 1996
	case DEVICE_ID_5764:
1922 1997
	case DEVICE_ID_5714C:
1923 1998
	case DEVICE_ID_5714S:
......
2023 2098

  
2024 2099
	cidp->msi_enabled = B_FALSE;
2025 2100

  
2101
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) >
2102
	    MHCR_CHIP_ASIC_REV_PRODID ||
2103
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2104
	    MHCR_CHIP_ASIC_REV_5906 ||
2105
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2106
	    MHCR_CHIP_ASIC_REV_5700 ||
2107
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2108
	    MHCR_CHIP_ASIC_REV_5701 ||
2109
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2110
	    MHCR_CHIP_ASIC_REV_5750)
2111
		/*
2112
		 * Just a plain reset; the "check" code breaks these chips
2113
		 */
2114
		cidp->flags |= CHIP_FLAG_NO_CHECK_RESET;
2115

  
2026 2116
	switch (cidp->device) {
2027 2117
	case DEVICE_ID_5717:
2028 2118
	case DEVICE_ID_5718:
2119
	case DEVICE_ID_5719:
2120
	case DEVICE_ID_5720:
2029 2121
	case DEVICE_ID_5724:
2030 2122
		if (cidp->device == DEVICE_ID_5717)
2031 2123
			cidp->chip_label = 5717;
2032 2124
		else if (cidp->device == DEVICE_ID_5718)
2033 2125
			cidp->chip_label = 5718;
2126
		else if (cidp->device == DEVICE_ID_5719)
2127
			cidp->chip_label = 5719;
2128
		else if (cidp->device == DEVICE_ID_5720)
2129
			cidp->chip_label = 5720;
2034 2130
		else
2035 2131
			cidp->chip_label = 5724;
2036 2132
		cidp->msi_enabled = bge_enable_msi;
......
2044 2140
		cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2045 2141
		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2046 2142
		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2047
		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2143
		cidp->recv_slots = BGE_RECV_SLOTS_5717;
2048 2144
		cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2049 2145
		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2050 2146
		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
......
2220 2316
	case DEVICE_ID_5723:
2221 2317
	case DEVICE_ID_5761:
2222 2318
	case DEVICE_ID_5761E:
2319
	case DEVICE_ID_5761S:
2320
	case DEVICE_ID_5761SE:
2321
	case DEVICE_ID_5784M:
2322
	case DEVICE_ID_57760:
2223 2323
	case DEVICE_ID_57780:
2324
	case DEVICE_ID_57788:
2325
	case DEVICE_ID_57790:
2224 2326
		cidp->msi_enabled = bge_enable_msi;
2225 2327
		/*
2226 2328
		 * We don't use MSI for BCM5764 and BCM5785, as the
......
2234 2336
			cidp->chip_label = 5723;
2235 2337
		else if (cidp->device == DEVICE_ID_5764)
2236 2338
			cidp->chip_label = 5764;
2339
		else if (cidp->device == DEVICE_ID_5784M)
2340
			cidp->chip_label = 5784;
2237 2341
		else if (cidp->device == DEVICE_ID_5785)
2238 2342
			cidp->chip_label = 5785;
2343
		else if (cidp->device == DEVICE_ID_57760)
2344
			cidp->chip_label = 57760;
2239 2345
		else if (cidp->device == DEVICE_ID_57780)
2240 2346
			cidp->chip_label = 57780;
2347
		else if (cidp->device == DEVICE_ID_57788)
2348
			cidp->chip_label = 57788;
2349
		else if (cidp->device == DEVICE_ID_57790)
2350
			cidp->chip_label = 57790;
2241 2351
		else
2242 2352
			cidp->chip_label = 5761;
2243 2353
		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
......
3401 3511
		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3402 3512
			MHCR_ENABLE_TAGGED_STATUS_MODE |
3403 3513
			MHCR_MASK_INTERRUPT_MODE |
3404
			MHCR_MASK_PCI_INT_OUTPUT |
3405 3514
			MHCR_CLEAR_INTERRUPT_INTA |
3406 3515
			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3407 3516
			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3517

  
3518
		if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3519
			mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3520

  
3408 3521
		if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3409 3522
			pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3410 3523
					0);
3524
#else
3525
		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3526
			MHCR_ENABLE_TAGGED_STATUS_MODE |
3527
			MHCR_MASK_INTERRUPT_MODE |
3528
			MHCR_MASK_PCI_INT_OUTPUT |
3529
			MHCR_CLEAR_INTERRUPT_INTA;
3530
#endif
3411 3531
		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3412 3532
		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3413 3533
			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3414 3534
			MEMORY_ARBITER_ENABLE);
3415
#endif
3416 3535
		if (asf_mode == ASF_MODE_INIT) {
3417 3536
			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3418 3537
		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
......
3436 3555

  
3437 3556
	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3438 3557
	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3558
	    MHCR_ENABLE_PCI_STATE_WRITE |
3439 3559
	    MHCR_MASK_INTERRUPT_MODE |
3440
	    MHCR_MASK_PCI_INT_OUTPUT |
3441 3560
	    MHCR_CLEAR_INTERRUPT_INTA;
3561

  
3562
	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3563
		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3564

  
3442 3565
#ifdef  _BIG_ENDIAN
3443 3566
	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3444 3567
#endif  /* _BIG_ENDIAN */
......
3449 3572
	if (bgep->asf_enabled)
3450 3573
		bgep->asf_wordswapped = B_FALSE;
3451 3574
#endif
3575

  
3576
	if (DEVICE_IS_5755_PLUS(bgep) ||
3577
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3578
	    MHCR_CHIP_ASIC_REV_5752)
3579
		bge_reg_put32(bgep, GRC_FASTBOOT_PC, 0);
3580

  
3452 3581
	/*
3453 3582
	 * NVRAM Corruption Workaround
3454 3583
	 */
......
3508 3637
#else
3509 3638
	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3510 3639
#endif	/* _BIG_ENDIAN */
3640
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3641
	    MHCR_CHIP_ASIC_REV_5720)
3642
		modeflags |=
3643
		    MODE_BYTE_SWAP_B2HRX_DATA | MODE_WORD_SWAP_B2HRX_DATA |
3644
		    MODE_B2HRX_ENABLE | MODE_HTX2B_ENABLE;
3511 3645
#ifdef BGE_IPMI_ASF
3512 3646
	if (bgep->asf_enabled)
3513 3647
		modeflags |= MODE_HOST_STACK_UP;
......
3592 3726
	 */
3593 3727
	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3594 3728

  
3729
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3730
	    MHCR_CHIP_ASIC_REV_5720) {
3731
		uint32_t regval = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
3732
		bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
3733
		    regval & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
3734
	}
3735

  
3595 3736
	/*
3596 3737
	 * Step 21: restore cache-line-size, latency timer, and
3597 3738
	 * subsystem ID registers to their original values (not
......
3818 3959
	/*
3819 3960
	 * Steps 34-36: enable buffer manager & internal h/w queues
3820 3961
	 */
3821
	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3822
	    STATE_MACHINE_ATTN_ENABLE_BIT))
3962

  
3963
	regval = STATE_MACHINE_ATTN_ENABLE_BIT;
3964
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3965
	    MHCR_CHIP_ASIC_REV_5719)
3966
		regval |= BUFF_MGR_NO_TX_UNDERRUN;
3967
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3968
	    MHCR_CHIP_ASIC_REV_5717 ||
3969
	    bgep->chipid.asic_rev == MHCR_CHIP_REV_5719_A0 ||
3970
	    bgep->chipid.asic_rev == MHCR_CHIP_REV_5720_A0)
3971
		regval |= BUFF_MGR_MBUF_LOW_ATTN_ENABLE;
3972
	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
3823 3973
		retval = DDI_FAILURE;
3824 3974
	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3825 3975
		retval = DDI_FAILURE;
......
3913 4063
	/*
3914 4064
	 * Step 50: configure the IPG et al
3915 4065
	 */
3916
	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
4066
	regval = MAC_TX_LENGTHS_DEFAULT;
4067
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)
4068
	    == MHCR_CHIP_ASIC_REV_5720)
4069
		regval |= bge_reg_get32(bgep, MAC_TX_LENGTHS_REG) &
4070
		    (MAC_TX_LENGTHS_JMB_FRM_LEN_MSK |
4071
		    MAC_TX_LENGTHS_CNT_DWN_VAL_MSK);
4072
	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, regval);
3917 4073

  
3918 4074
	/*
3919 4075
	 * Step 51: configure the default Rx Return Ring
......
4068 4224
			retval = DDI_FAILURE;
4069 4225
	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4070 4226
	    ALL_DMA_ATTN_BITS;
4071
	if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4072
	    MHCR_CHIP_ASIC_REV_5755) ||
4073
	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4074
	    MHCR_CHIP_ASIC_REV_5723) ||
4075
	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4076
	    MHCR_CHIP_ASIC_REV_5906)) {
4227
	if (DEVICE_IS_5755_PLUS(bgep))
4077 4228
		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4078
	}
4079 4229
	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4080 4230
	    dma_wrprio))
4081 4231
		retval = DDI_FAILURE;
4232
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4233
	    MHCR_CHIP_ASIC_REV_5761 ||
4234
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4235
	    MHCR_CHIP_ASIC_REV_5784 ||
4236
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4237
	    MHCR_CHIP_ASIC_REV_5785 ||
4238
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4239
	    MHCR_CHIP_ASIC_REV_57780 ||
4240
	    DEVICE_IS_57765_PLUS(bgep)) {
4241
		regval = bge_reg_get32(bgep, READ_DMA_RESERVED_CONTROL_REG);
4242
		if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4243
		    MHCR_CHIP_ASIC_REV_5719 ||
4244
		    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4245
		    MHCR_CHIP_ASIC_REV_5720) {
4246
			regval &= ~(RDMA_RSRVCTRL_TXMRGN_MASK |
4247
			    RDMA_RSRVCTRL_FIFO_LWM_MASK |
4248
			    RDMA_RSRVCTRL_FIFO_HWM_MASK);
4249
			regval |= RDMA_RSRVCTRL_TXMRGN_320B |
4250
			    RDMA_RSRVCTRL_FIFO_LWM_1_5K |
4251
			    RDMA_RSRVCTRL_FIFO_HWM_1_5K;
4252
		}
4253
		bge_reg_put32(bgep, READ_DMA_RESERVED_CONTROL_REG,
4254
		    regval | RDMA_RSRVCTRL_FIFO_OFLW_FIX);
4255
	}
4082 4256
	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4083 4257
	    DEVICE_5717_SERIES_CHIPSETS(bgep))
4084 4258
		bge_dma_rdprio = 0;
4259
	regval = bge_dma_rdprio << DMA_PRIORITY_SHIFT;
4260
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4261
	    MHCR_CHIP_ASIC_REV_5720)
4262
		regval |= bge_reg_get32(bgep, READ_DMA_MODE_REG) &
4263
		    DMA_H2BNC_VLAN_DET;
4085 4264
	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4086
	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
4265
	    regval | ALL_DMA_ATTN_BITS))
4087 4266
		retval = DDI_FAILURE;
4088 4267
	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4089 4268
	    STATE_MACHINE_ATTN_ENABLE_BIT))
......
4116 4295
	 * Step 88: download firmware -- doesn't apply
4117 4296
	 * Steps 89-90: enable Transmit & Receive MAC Engines
4118 4297
	 */
4119
	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
4298
	if (DEVICE_IS_5755_PLUS(bgep) ||
4299
	    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4300
	    MHCR_CHIP_ASIC_REV_5906) {
4301
		regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
4302
		regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX;
4303
	} else {
4304
		regval = 0;
4305
	}
4306
	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4307
	    MHCR_CHIP_ASIC_REV_5720) {
4308
		regval &= ~(TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
4309
		    TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
4310
		regval |= bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG) &
4311
		    (TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
4312
		    TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
4313
	}
4314
	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
4120 4315
		retval = DDI_FAILURE;
4121 4316
#ifdef BGE_IPMI_ASF
4122 4317
	if (!bgep->asf_enabled) {
......
4219 4414
	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4220 4415
		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4221 4416
		    bgep->chipid.mask_pci_int);
4222

  
4223 4417
	/*
4224 4418
	 * All done!
4225 4419
	 */
......
5968 6162
}
5969 6163

  
5970 6164
#endif /* BGE_IPMI_ASF */
6165

  
5971
-- usr/src/uts/common/io/bge/bge_impl.h	2014-02-06 19:04:47.000000000 -0500
6166
++ usr/src/uts/common/io/bge/bge_impl.h	2014-02-08 12:19:12.294970700 -0500
......
23 23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24
 */
25 25

  
26
/*
27
 * Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
28
 */
29

  
26 30
#ifndef _BGE_IMPL_H
27 31
#define	_BGE_IMPL_H
28 32

  
......
605 609
	uint8_t			latency;	/* latency-timer	*/
606 610

  
607 611
	uint8_t			flags;
612
	uint32_t		chip_type;	/* see CHIP_TYPE_ in bge_hw.h */
608 613
	uint16_t		chip_label;	/* numeric part only	*/
609 614
						/* (e.g. 5703/5794/etc)	*/
610 615
	uint32_t		mbuf_base;	/* Mbuf pool parameters */
......
640 645
	uint32_t		mask_pci_int;
641 646
} chip_id_t;
642 647

  
643
#define	CHIP_FLAG_SUPPORTED	0x80
644
#define	CHIP_FLAG_SERDES	0x40
645
#define	CHIP_FLAG_PARTIAL_CSUM	0x20
646
#define	CHIP_FLAG_NO_JUMBO	0x1
648
#define	CHIP_FLAG_SUPPORTED	 0x80
649
#define	CHIP_FLAG_SERDES	 0x40
650
#define	CHIP_FLAG_PARTIAL_CSUM	 0x20
651
#define	CHIP_FLAG_NO_CHECK_RESET 0x2
652
#define	CHIP_FLAG_NO_JUMBO	 0x1
647 653

  
648 654
/*
649 655
 * Collection of physical-layer functions to:
......
1292 1298
#endif
1293 1299

  
1294 1300
#endif	/* _BGE_IMPL_H */
1301

  
1302

  
1295
-- usr/src/uts/common/io/bge/bge_main2.c	2014-02-06 19:04:47.000000000 -0500
1303
++ usr/src/uts/common/io/bge/bge_main2.c	2014-02-08 12:39:51.136925700 -0500
......
23 23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24
 */
25 25

  
26
/*
27
 * Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
28
 */
29

  
26 30
#include "bge_impl.h"
27 31
#include <sys/sdt.h>
28 32
#include <sys/mac_provider.h>
......
3211 3215
	 */
3212 3216
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3213 3217
		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3218
#else
3219
	mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS |
3220
	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3221
	    MHCR_MASK_INTERRUPT_MODE |
3222
	    MHCR_MASK_PCI_INT_OUTPUT |
3223
	    MHCR_CLEAR_INTERRUPT_INTA;
3224
#endif
3214 3225
	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcrValue);
3215 3226
	bge_ind_put32(bgep, MEMORY_ARBITER_MODE_REG,
3216 3227
	    bge_ind_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3217 3228
	    MEMORY_ARBITER_ENABLE);
3218
#else
3219
	mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
3220
#endif
3221 3229
	if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) {
3222 3230
		bgep->asf_wordswapped = B_TRUE;
3223 3231
	} else {
3224
-- usr/src/uts/common/io/bge/bge_mii.c	2014-02-06 19:04:47.000000000 -0500
3232
++ usr/src/uts/common/io/bge/bge_mii.c	2014-02-08 12:19:12.377979600 -0500
......
23 23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24
 */
25 25

  
26
/*
27
 * Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
28
 */
29

  
26 30
#include "bge_impl.h"
27 31

  
28 32
/*
......
207 211
{
208 212
	uint16_t control;
209 213
	uint_t count;
214
	boolean_t ret = B_FALSE;
210 215

  
211 216
	BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep));
212 217

  
......
221 226
	}
222 227

  
223 228
	/*
224
	 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
229
	 * Set the PHY RESET bit, then wait up to 50 ms for it to self-clear
225 230
	 */
226 231
	bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
227
	for (count = 0; ++count < 1000; ) {
228
		drv_usecwait(5);
232
	for (count = 0; ++count < 5000; ) {
229 233
		control = bge_mii_get16(bgep, MII_CONTROL);
230
		if (BIC(control, MII_CONTROL_RESET))
231
			return (B_TRUE);
234
		if (BIC(control, MII_CONTROL_RESET)) {
235
			drv_usecwait(40);
236
			ret = B_TRUE;
237
			break;
238
		}
239
		drv_usecwait(10);
232 240
	}
233 241

  
234
	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
242
	if (ret == B_TRUE && DEVICE_5906_SERIES_CHIPSETS(bgep))
235 243
		(void) bge_adj_volt_5906(bgep);
236 244

  
237
	BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control));
245
	if (ret == B_FALSE)
246
		BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control));
238 247

  
239
	return (B_FALSE);
248
	return (ret);
240 249
}
241 250

  
242 251
/*
......
541 550

  
542 551
	ASSERT(mutex_owned(bgep->genlock));
543 552

  
544
	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
545
	default:
546
		/*
547
		 * Shouldn't happen; it means we don't recognise this chip.
548
		 * It's probably a new one, so we'll try our best anyway ...
549
		 */
550
	case MHCR_CHIP_ASIC_REV_5703:
551
	case MHCR_CHIP_ASIC_REV_5704:
552
	case MHCR_CHIP_ASIC_REV_5705:
553
	case MHCR_CHIP_ASIC_REV_5752:
554
	case MHCR_CHIP_ASIC_REV_5714:
555
	case MHCR_CHIP_ASIC_REV_5715:
556
		reset_ok = bge_phy_reset_and_check(bgep);
557
		break;
558

  
559
	case MHCR_CHIP_ASIC_REV_5906:
560
	case MHCR_CHIP_ASIC_REV_5700:
561
	case MHCR_CHIP_ASIC_REV_5701:
562
	case MHCR_CHIP_ASIC_REV_5723:
563
	case MHCR_CHIP_ASIC_REV_5721_5751:
564
		/*
565
		 * Just a plain reset; the "check" code breaks these chips
566
		 */
553
	if (bgep->chipid.flags & CHIP_FLAG_NO_CHECK_RESET) {
567 554
		reset_ok = bge_phy_reset(bgep);
568 555
		if (!reset_ok)
569 556
			bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
570
		break;
557
	} else {
558
		reset_ok = bge_phy_reset_and_check(bgep);
571 559
	}
560

  
572 561
	if (!reset_ok) {
573 562
		BGE_REPORT((bgep, "PHY failed to reset correctly"));
574 563
		return (DDI_FAILURE);
......
590 579

  
591 580
	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
592 581
	case MHCR_CHIP_ASIC_REV_5705:
593
	case MHCR_CHIP_ASIC_REV_5721_5751:
582
	case MHCR_CHIP_ASIC_REV_5750:
594 583
		bge_phy_bit_err_fix(bgep);
595 584
		break;
596 585
	}
......
1507 1496
	 */
1508 1497
	bgep->phy_mii_addr = 1;
1509 1498
	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1510
		int regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
1511
		if (regval & CPMU_STATUS_FUN_NUM)
1512
			bgep->phy_mii_addr += 1;
1499
		uint32_t regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
1500
		if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
1501
		    MHCR_CHIP_ASIC_REV_5719 ||
1502
		    MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
1503
		    MHCR_CHIP_ASIC_REV_5720) {
1504
			bgep->phy_mii_addr +=
1505
			    (regval & CPMU_STATUS_FUN_NUM_5719) >>
1506
			    CPMU_STATUS_FUN_NUM_5719_SHIFT;
1507
		} else {
1508
			bgep->phy_mii_addr +=
1509
			    (regval & CPMU_STATUS_FUN_NUM_5717) ? 1 : 0;
1510
		}
1513 1511
		regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
1514 1512
		if (regval & MEDIA_SELECTION_MODE)
1515 1513
			bgep->phy_mii_addr += 7;
1516 1514
	}
1517

  
1518 1515
	if (bge_phy_probe(bgep)) {
1519 1516
		bgep->chipid.flags &= ~CHIP_FLAG_SERDES;
1520 1517
		bgep->physops = &copper_ops;
......
1621 1618

  
1622 1619
	return (B_TRUE);
1623 1620
}
1621

  
1622

  
1624
-- usr/src/pkg/manifests/driver-network-bge.mf	2014-02-06 19:04:47.000000000 -0500
1623
++ usr/src/pkg/manifests/driver-network-bge.mf	2014-02-08 11:48:45.315941700 -0500
......
24 24
#
25 25

  
26 26
#
27
# Copyright 2014 Nexenta Systems, Inc.  All rights reserved.
28
#
29

  
27 30
# The default for payload-bearing actions in this package is to appear in the
28 31
# global zone only.  See the include file for greater detail, as well as
29 32
# information about overriding the defaults.
......
57 60
    alias=pci14e4,1649 \
58 61
    alias=pci14e4,1653 \
59 62
    alias=pci14e4,1654 \
63
    alias=pci14e4,1657 \
60 64
    alias=pci14e4,1659 \
61 65
    alias=pci14e4,165d \
62 66
    alias=pci14e4,165e \
67
    alias=pci14e4,165f \
63 68
    alias=pci14e4,1668 \
64 69
    alias=pci14e4,1669 \
65 70
    alias=pci14e4,166a \
......
79 84
    alias=pci14e4,16c7 \
80 85
    alias=pciex14e4,1655 \
81 86
    alias=pciex14e4,1656 \
87
    alias=pciex14e4,1657 \
82 88
    alias=pciex14e4,165a \
83 89
    alias=pciex14e4,165b \
84 90
    alias=pciex14e4,165c \
91
    alias=pciex14e4,165f \
85 92
    alias=pciex14e4,1673 \
86 93
    alias=pciex14e4,1674 \
87 94
    alias=pciex14e4,1677 \
......
90 97
    alias=pciex14e4,1680 \
91 98
    alias=pciex14e4,1681 \
92 99
    alias=pciex14e4,1684 \
100
    alias=pciex14e4,1688 \
101
    alias=pciex14e4,1689 \
102
    alias=pciex14e4,1690 \
103
    alias=pciex14e4,1691 \
93 104
    alias=pciex14e4,1692 \
105
    alias=pciex14e4,1694 \
106
    alias=pciex14e4,1698 \
94 107
    alias=pciex14e4,169d \
95 108
    alias=pciex14e4,16fd \
96 109
    alias=pciex14e4,1713
......
133 146
license lic_CDDL license=lic_CDDL
134 147
license usr/src/uts/common/io/bge/THIRDPARTYLICENSE \
135 148
    license=usr/src/uts/common/io/bge/THIRDPARTYLICENSE
149

  
150

  
(1-1/10)