Project

General

Profile

Feature #3446 » bge_illumos_kmays_021414-01.patch

Ken Mays, 2014-02-14 01:01 AM

View differences:

usr/src/uts/common/io/bge/bge_hw.h 2013-06-28 19:01:04.000000000 -0400
20 20
 */
21 21

  
22 22
/*
23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23
 * Copyright (c) 2010-2013, by Broadcom, Inc.
24
 * All Rights Reserved.
25
 */
26

  
27
/*
28
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29
 * All rights reserved.
24 30
 */
25 31

  
26 32
#ifndef _BGE_HW_H
......
64 70
#define	DEVICE_ID_5705C			0x1653
65 71
#define	DEVICE_ID_5705_2		0x1654
66 72
#define	DEVICE_ID_5717			0x1655
73
#define	DEVICE_ID_5717_C0		0x1665
67 74
#define	DEVICE_ID_5718			0x1656
75
#define	DEVICE_ID_5719			0x1657
76
#define	DEVICE_ID_5720			0x165f
68 77
#define	DEVICE_ID_5724			0x165c
78
#define	DEVICE_ID_5725			0x1643
79
#define	DEVICE_ID_5727			0x16f3
69 80
#define	DEVICE_ID_5705M			0x165d
70 81
#define	DEVICE_ID_5705MA3		0x165e
71 82
#define	DEVICE_ID_5705F			0x166e
......
187 198
		(bgep->chipid.device == DEVICE_ID_5789))
188 199

  
189 200
#define	DEVICE_5717_SERIES_CHIPSETS(bgep) \
190
		(bgep->chipid.device == DEVICE_ID_5717) ||\
201
		((bgep->chipid.device == DEVICE_ID_5717) ||\
191 202
		(bgep->chipid.device == DEVICE_ID_5718) ||\
192
		(bgep->chipid.device == DEVICE_ID_5724)
203
		(bgep->chipid.device == DEVICE_ID_5719) ||\
204
		(bgep->chipid.device == DEVICE_ID_5720) ||\
205
		(bgep->chipid.device == DEVICE_ID_5724))
206

  
207
#define	DEVICE_5725_SERIES_CHIPSETS(bgep) \
208
		((bgep->chipid.device == DEVICE_ID_5725) ||\
209
		(bgep->chipid.device == DEVICE_ID_5727))
193 210

  
194 211
#define	DEVICE_5723_SERIES_CHIPSETS(bgep) \
195 212
		((bgep->chipid.device == DEVICE_ID_5723) ||\
......
230 247
#define	MHCR_ENABLE_INDIRECT_ACCESS	0x00000080
231 248
#define	MHCR_ENABLE_REGISTER_WORD_SWAP	0x00000040
232 249
#define	MHCR_ENABLE_CLOCK_CONTROL_WRITE	0x00000020
233
#define	MHCR_ENABLE_PCI_STATE_WRITE	0x00000010
250
#define	MHCR_ENABLE_PCI_STATE_RW	0x00000010
234 251
#define	MHCR_ENABLE_ENDIAN_WORD_SWAP	0x00000008
235 252
#define	MHCR_ENABLE_ENDIAN_BYTE_SWAP	0x00000004
236 253
#define	MHCR_MASK_PCI_INT_OUTPUT	0x00000002
237 254
#define	MHCR_CLEAR_INTERRUPT_INTA	0x00000001
255
#define	MHCR_BOUNDARY_CHECK		0x00002000
256
#define	MHCR_TLP_MINOR_ERR_TOLERANCE	0x00008000
238 257

  
239 258
#define	MHCR_CHIP_REV_5700_B0		0x71000000
240 259
#define	MHCR_CHIP_REV_5700_B2		0x71020000
......
304 323
#define	MHCR_CHIP_REV_5906_A1		0xc0010000
305 324
#define	MHCR_CHIP_REV_5906_A2		0xc0020000
306 325

  
307
#define	MHCR_CHIP_REV_5723_A0		0xf0000000
308
#define	MHCR_CHIP_REV_5723_A1		0xf0010000
309
#define	MHCR_CHIP_REV_5723_A2		0xf0020000
310
#define	MHCR_CHIP_REV_5723_B0		0xf1000000
326
#define	CHIP_ASIC_REV_USE_PROD_ID_REG	0xf0000000
327
#define MHCR_CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev & 0xf0000000)
328
#define CHIP_ASIC_REV_PROD_ID(bgep) ((bgep)->chipid.asic_rev_prod_id)
329
#define CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev_prod_id >> 12)
311 330

  
312
#define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) & 0xf0000000)
313 331
#define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
314 332
#define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
315 333
#define	MHCR_CHIP_ASIC_REV_5703		(0x1 << 28)
......
323 341
#define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
324 342
#define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
325 343
#define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
344
/* (0xf << 28) touches all 5717 and 5725 series as well (OK) */
326 345
#define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
327 346

  
347
#define	CHIP_ASIC_REV_5723		0x5784
348
#define	CHIP_ASIC_REV_5761		0x5761
349
#define	CHIP_ASIC_REV_5785		0x5785
350
#define	CHIP_ASIC_REV_57780		0x57780
351

  
352
#define	CHIP_ASIC_REV_5717		0x5717
353
#define	CHIP_ASIC_REV_5719		0x5719
354
#define	CHIP_ASIC_REV_5720		0x5720
355
#define	CHIP_ASIC_REV_5762		0x5762 /* 5725/5727 */
356

  
357
#define	CHIP_ASIC_REV_PROD_ID_REG	0x000000bc
358
#define	CHIP_ASIC_REV_PROD_ID_GEN2_REG	0x000000f4
359

  
360
#define	CHIP_ASIC_REV_5717_B0		0x05717100
361
#define	CHIP_ASIC_REV_5717_C0		0x05717200
362
#define	CHIP_ASIC_REV_5718_B0		0x05717100
363
#define	CHIP_ASIC_REV_5719_A0		0x05719000
364
#define	CHIP_ASIC_REV_5719_A1		0x05719001
365
#define	CHIP_ASIC_REV_5720_A0		0x05720000
366
#define	CHIP_ASIC_REV_5725_A0		0x05762000
367
#define	CHIP_ASIC_REV_5727_B0		0x05762100
328 368

  
329 369
/*
330 370
 * PCI DMA read/write Control Register, in PCI config space
......
374 414
 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
375 415
 */
376 416
#define	PCI_CONF_BGE_PCISTATE		0x70
417
#define	PCISTATE_ALLOW_APE_CTLSPC_WR	0x00010000
418
#define	PCISTATE_ALLOW_APE_SHMEM_WR	0x00020000
419
#define	PCISTATE_ALLOW_APE_PSPACE_WR	0x00040000
377 420
#define	PCISTATE_RETRY_SAME_DMA		0x00002000
378 421
#define	PCISTATE_FLAT_VIEW		0x00000100
379 422
#define	PCISTATE_EXT_ROM_RETRY		0x00000040
......
458 501
 */
459 502
#define	PCI_CONF_DEV_CTRL		0xd8
460 503
#define	PCI_CONF_DEV_CTRL_5723		0xd4
504
#define	PCI_CONF_DEV_CTRL_5717		0xb4
505
#define	READ_REQ_SIZE_MASK		0x7000
461 506
#define	READ_REQ_SIZE_MAX		0x5000
507
#define	READ_REQ_SIZE_2K 		0x4000
462 508
#define	DEV_CTRL_NO_SNOOP		0x0800
463 509
#define	DEV_CTRL_RELAXED		0x0010
464 510

  
......
497 543
#define	NIC_MEM_SHADOW_SEND_7_8		0x7000		/* bogus	*/
498 544
#define	NIC_MEM_SHADOW_SEND_9_16	0x8000		/* bogus	*/
499 545
#define	NIC_MEM_SHADOW_BUFF_STD		0x6000
500
#define	NIC_MEM_SHADOW_BUFF_STD_5717		0x40000
546
#define	NIC_MEM_SHADOW_BUFF_STD_5717	0x40000
501 547
#define	NIC_MEM_SHADOW_BUFF_JUMBO	0x7000
502 548
#define	NIC_MEM_SHADOW_BUFF_MINI	0x8000		/* bogus	*/
503 549
#define	NIC_MEM_SHADOW_SEND_RING(ring, nslots)	(0x4000 + 4*(ring)*(nslots))
......
540 586
#define	HOST_COALESCE_MODE_REG		0x3c00
541 587
#define	MEMORY_ARBITER_MODE_REG		0x4000
542 588
#define	BUFFER_MANAGER_MODE_REG		0x4400
589
#define	BUFFER_MANAGER_MODE_NO_TX_UNDERRUN	0x80000000
590
#define	BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE	0x00000010
543 591
#define	READ_DMA_MODE_REG		0x4800
544 592
#define	WRITE_DMA_MODE_REG		0x4c00
545 593
#define	DMA_COMPLETION_MODE_REG		0x6400
594
#define	FAST_BOOT_PC			0x6894
595

  
596
#define	RDMA_RSRV_CTRL_REG		0x4900
597
#define	RDMA_RSRV_CTRL_REG2		0x4890
598
#define	RDMA_RSRV_CTRL_FIFO_OFLW_FIX	0x00000004
599
#define	RDMA_RSRV_CTRL_FIFO_LWM_1_5K	0x00000c00
600
#define	RDMA_RSRV_CTRL_FIFO_LWM_MASK	0x00000ff0
601
#define	RDMA_RSRV_CTRL_FIFO_HWM_1_5K	0x000c0000
602
#define	RDMA_RSRV_CTRL_FIFO_HWM_MASK	0x000ff000
603
#define	RDMA_RSRV_CTRL_TXMRGN_320B	0x28000000
604
#define	RDMA_RSRV_CTRL_TXMRGN_MASK	0xffe00000
605

  
606
#define	RDMA_CORR_CTRL_REG		0x4910
607
#define	RDMA_CORR_CTRL_REG2		0x48a0
608
#define	RDMA_CORR_CTRL_BLEN_BD_4K	0x00030000
609
#define	RDMA_CORR_CTRL_BLEN_LSO_4K	0x000c0000
610
#define RDMA_CORR_CTRL_TX_LENGTH_WA	0x02000000
611

  
612
#define BGE_NUM_RDMA_CHANNELS		4
613
#define BGE_RDMA_LENGTH			0x4be0
546 614

  
547 615
/*
548 616
 * Other bits in some of the above state machine control registers
......
552 620
 * Transmit MAC Mode Register
553 621
 * (TRANSMIT_MAC_MODE_REG, 0x045c)
554 622
 */
623
#define	TRANSMIT_MODE_MBUF_LOCKUP_FIX	0x00000100
555 624
#define	TRANSMIT_MODE_LONG_PAUSE	0x00000040
556 625
#define	TRANSMIT_MODE_BIG_BACKOFF	0x00000020
557 626
#define	TRANSMIT_MODE_FLOW_CONTROL	0x00000010
......
682 751
 * Ethernet MAC Mode Register
683 752
 */
684 753
#define	ETHERNET_MAC_MODE_REG		0x0400
754
#define	ETHERNET_MODE_APE_TX_EN		0x10000000
755
#define	ETHERNET_MODE_APE_RX_EN		0x08000000
685 756
#define	ETHERNET_MODE_ENABLE_FHDE	0x00800000
686 757
#define	ETHERNET_MODE_ENABLE_RDE	0x00400000
687 758
#define	ETHERNET_MODE_ENABLE_TDE	0x00200000
......
970 1041
#define	SERDES_STATUS_COMMA_DETECTED	0x00000100
971 1042
#define	SERDES_STATUS_RXSTAT		0x000000ff
972 1043

  
1044
/* 5780/5714 only */
1045
#define SERDES_RX_CONTROL		0x000005b0
1046
#define SERDES_RX_CONTROL_SIG_DETECT	0x00000400
1047

  
973 1048
/*
974
 * SGMII Status Register (5717/5718 only)
1049
 * SGMII Status Register (5717/18/19/20 only)
975 1050
 */
976 1051
#define	SGMII_STATUS_REG	0x5B4
977 1052
#define	MEDIA_SELECTION_MODE	0x00000100
......
1069 1144
#define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
1070 1145

  
1071 1146
/*
1072
 * CPMU registers (5717/5718 only)
1147
 * CPMU registers (5717/18/19/20 only)
1073 1148
 */
1074
#define	CPMU_STATUS_REG	0x362c
1075
#define	CPMU_STATUS_FUN_NUM	0x20000000
1149
#define	CPMU_CLCK_ORIDE_REG		0x3624
1150
#define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
1151
#define	CPMU_STATUS_REG			0x362c
1152
#define	CPMU_STATUS_FUNC_NUM		0x20000000
1153
#define	CPMU_STATUS_FUNC_NUM_SHIFT	29
1154
#define	CPMU_STATUS_FUNC_NUM_5719 	0xc0000000
1155
#define	CPMU_STATUS_FUNC_NUM_5719_SHIFT	30
1156

  
1157
/*
1158
 * EEE registers (5718/19/20 only)
1159
 */
1160
#define	EEE_MODE_REG			0x36b0
1161
#define	EEE_MODE_APE_TX_DET_EN		0x00000004
1162
#define	EEE_MODE_ERLY_L1_XIT_DET	0x00000008
1163
#define	EEE_MODE_SND_IDX_DET_EN		0x00000040
1164
#define	EEE_MODE_LPI_ENABLE		0x00000080
1165
#define	EEE_MODE_LPI_IN_TX		0x00000100
1166
#define	EEE_MODE_LPI_IN_RX		0x00000200
1167
#define	EEE_MODE_EEE_ENABLE		0x00100000
1168

  
1169
#define	EEE_DEBOUNCE_T1_CONTROL_REG	0x36b4
1170
#define	EEE_DEBOUNCE_T1_PCIEXIT_2047US	0x07ff0000
1171
#define	EEE_DEBOUNCE_T1_LNKIDLE_2047US	0x000007ff
1172

  
1173
#define	EEE_DEBOUNCE_T2_CONTROL_REG	0x36b8
1174
#define	EEE_DEBOUNCE_T2_APE_TX_2047US	0x07ff0000
1175
#define	EEE_DEBOUNCE_T2_TXIDXEQ_2047US	0x000007ff
1176

  
1177
#define	EEE_LINK_IDLE_CONTROL_REG	0x36bc
1178
#define	EEE_LINK_IDLE_PCIE_NL0		0x01000000
1179
#define	EEE_LINK_IDLE_UART_IDL		0x00000004
1180
#define	EEE_LINK_IDLE_APE_TX_MT		0x00000002
1181

  
1182
#define	EEE_CONTROL_REG			0x36d0
1183
#define	EEE_CONTROL_EXIT_16_5_US	0x0000019d
1184
#define	EEE_CONTROL_EXIT_36_US		0x00000384
1185
#define	EEE_CONTROL_EXIT_20_1_US	0x000001f8
1186

  
1187
/* Clause 45 expansion registers */
1188
#define	EEE_CL45_D7_RESULT_STAT			0x803e
1189
#define	EEE_CL45_D7_RESULT_STAT_LP_100TX	0x0002
1190
#define	EEE_CL45_D7_RESULT_STAT_LP_1000T	0x0004
1191

  
1192
#define MDIO_MMD_AN			0x0007
1193
#define MDIO_AN_EEE_ADV			0x003c
1076 1194

  
1077 1195
/*
1078 1196
 * Host Coalescing Engine Control Registers
......
1259 1377
 * Miscellaneous Local Control Register (MLCR)
1260 1378
 */
1261 1379
#define	MISC_LOCAL_CONTROL_REG		0x6808
1380

  
1262 1381
#define	MLCR_PCI_CTRL_SELECT		0x10000000
1263 1382
#define	MLCR_LEGACY_PCI_MODE		0x08000000
1264 1383
#define	MLCR_AUTO_SEEPROM_ACCESS	0x01000000
1265 1384
#define	MLCR_SSRAM_CYCLE_DESELECT	0x00800000
1266 1385
#define	MLCR_SSRAM_TYPE			0x00400000
1267 1386
#define	MLCR_BANK_SELECT		0x00200000
1387

  
1388
#define	MLCR_SRAM_SIZE_16M		0x00180000
1389
#define	MLCR_SRAM_SIZE_8M		0x00140000
1390
#define	MLCR_SRAM_SIZE_4M		0x00100000
1391
#define	MLCR_SRAM_SIZE_2M		0x000c0000
1392
#define	MLCR_SRAM_SIZE_1M		0x00080000
1393
#define	MLCR_SRAM_SIZE_512K		0x00040000
1394
#define	MLCR_SRAM_SIZE_256K		0x00000000
1268 1395
#define	MLCR_SRAM_SIZE_MASK		0x001c0000
1269
#define	MLCR_ENABLE_EXTERNAL_MEMORY	0x00020000
1270 1396

  
1397
#define	MLCR_ENABLE_EXTERNAL_MEMORY	0x00020000
1271 1398
#define	MLCR_MISC_PINS_OUTPUT_2		0x00010000
1399

  
1272 1400
#define	MLCR_MISC_PINS_OUTPUT_1		0x00008000
1273 1401
#define	MLCR_MISC_PINS_OUTPUT_0		0x00004000
1274 1402
#define	MLCR_MISC_PINS_OUTPUT_ENABLE_2	0x00002000
1275 1403
#define	MLCR_MISC_PINS_OUTPUT_ENABLE_1	0x00001000
1404

  
1276 1405
#define	MLCR_MISC_PINS_OUTPUT_ENABLE_0	0x00000800
1277 1406
#define	MLCR_MISC_PINS_INPUT_2		0x00000400	/* R/O	*/
1278 1407
#define	MLCR_MISC_PINS_INPUT_1		0x00000200	/* R/O	*/
1279 1408
#define	MLCR_MISC_PINS_INPUT_0		0x00000100	/* R/O	*/
1280 1409

  
1410
#define	MLCR_GPIO_OUTPUT3		0x00000080
1411
#define	MLCR_GPIO_OE3			0x00000040
1412
#define	MLCR_USE_EXT_SIG_DETECT		0x00000020	/* 5714/5780 only */
1413
#define	MLCR_GPIO_INPUT3		0x00000020
1414
#define	MLCR_GPIO_UART_SEL		0x00000010	/* 5755 only */
1415
#define	MLCR_USE_SIG_DETECT		0x00000010	/* 5714/5780 only */
1416

  
1281 1417
#define	MLCR_INT_ON_ATTN		0x00000008	/* R/W	*/
1282 1418
#define	MLCR_SET_INT			0x00000004	/* W/O	*/
1283 1419
#define	MLCR_CLR_INT			0x00000002	/* W/O	*/
......
1292 1428
 * just this fashion.  It has to be set as an OUTPUT and driven LOW to
1293 1429
 * enable writing.  Otherwise, the SEEPROM is protected.
1294 1430
 */
1295
#define	MLCR_DEFAULT			0x0101c000
1296
#define	MLCR_DEFAULT_5714		0x1901c000
1297
#define	MLCR_DEFAULT_5717		0x01000000
1431
#define	MLCR_DEFAULT			(MLCR_AUTO_SEEPROM_ACCESS | \
1432
					 MLCR_MISC_PINS_OUTPUT_2  | \
1433
					 MLCR_MISC_PINS_OUTPUT_1  | \
1434
					 MLCR_MISC_PINS_OUTPUT_0)
1435

  
1436
#define	MLCR_DEFAULT_5714		(MLCR_PCI_CTRL_SELECT     | \
1437
					 MLCR_LEGACY_PCI_MODE     | \
1438
					 MLCR_AUTO_SEEPROM_ACCESS | \
1439
					 MLCR_MISC_PINS_OUTPUT_2  | \
1440
					 MLCR_MISC_PINS_OUTPUT_1  | \
1441
					 MLCR_MISC_PINS_OUTPUT_0  | \
1442
					 MLCR_USE_SIG_DETECT)
1443

  
1444
#define	MLCR_DEFAULT_5717		(MLCR_AUTO_SEEPROM_ACCESS)
1298 1445

  
1299 1446
/*
1300 1447
 * Serial EEPROM Data/Address Registers (auto-access mode)
......
1351 1498
#define	NVM_CFG1_FLASH_MODE		0x00000001
1352 1499

  
1353 1500
#define	NVM_SW_ARBITRATION_REG		0x7020
1354
#define	NVM_READ_REQ3			0X00008000
1355
#define	NVM_READ_REQ2			0X00004000
1356
#define	NVM_READ_REQ1			0X00002000
1357
#define	NVM_READ_REQ0			0X00001000
1358
#define	NVM_WON_REQ3			0X00000800
1359
#define	NVM_WON_REQ2			0X00000400
1360
#define	NVM_WON_REQ1			0X00000200
1361
#define	NVM_WON_REQ0			0X00000100
1362
#define	NVM_RESET_REQ3			0X00000080
1363
#define	NVM_RESET_REQ2			0X00000040
1364
#define	NVM_RESET_REQ1			0X00000020
1365
#define	NVM_RESET_REQ0			0X00000010
1366
#define	NVM_SET_REQ3			0X00000008
1367
#define	NVM_SET_REQ2			0X00000004
1368
#define	NVM_SET_REQ1			0X00000002
1369
#define	NVM_SET_REQ0			0X00000001
1501
#define	NVM_READ_REQ3			0x00008000
1502
#define	NVM_READ_REQ2			0x00004000
1503
#define	NVM_READ_REQ1			0x00002000
1504
#define	NVM_READ_REQ0			0x00001000
1505
#define	NVM_WON_REQ3			0x00000800
1506
#define	NVM_WON_REQ2			0x00000400
1507
#define	NVM_WON_REQ1			0x00000200
1508
#define	NVM_WON_REQ0			0x00000100
1509
#define	NVM_RESET_REQ3			0x00000080
1510
#define	NVM_RESET_REQ2			0x00000040
1511
#define	NVM_RESET_REQ1			0x00000020
1512
#define	NVM_RESET_REQ0			0x00000010
1513
#define	NVM_SET_REQ3			0x00000008
1514
#define	NVM_SET_REQ2			0x00000004
1515
#define	NVM_SET_REQ1			0x00000002
1516
#define	NVM_SET_REQ0			0x00000001
1517

  
1518
#define	EEPROM_MAGIC			0x669955aa
1519
#define	EEPROM_MAGIC_FW			0xa5000000
1520
#define	EEPROM_MAGIC_FW_MSK		0xff000000
1521
#define	EEPROM_SB_FORMAT_MASK		0x00e00000
1522
#define	EEPROM_SB_FORMAT_1		0x00200000
1523
#define	EEPROM_SB_REVISION_MASK		0x001f0000
1524
#define	EEPROM_SB_REVISION_0		0x00000000
1525
#define	EEPROM_SB_REVISION_2		0x00020000
1526
#define	EEPROM_SB_REVISION_3		0x00030000
1527
#define	EEPROM_SB_REVISION_4		0x00040000
1528
#define	EEPROM_SB_REVISION_5		0x00050000
1529
#define	EEPROM_SB_REVISION_6		0x00060000
1530
#define	EEPROM_MAGIC_HW			0xabcd
1531
#define	EEPROM_MAGIC_HW_MSK		0xffff
1532

  
1533
#define	NVM_DIR_START		0x18
1534
#define	NVM_DIR_END		0x78
1535
#define	NVM_DIRENT_SIZE		0xc
1536
#define	NVM_DIRTYPE_SHIFT	24
1537
#define	NVM_DIRTYPE_LENMSK	0x003fffff
1538
#define	NVM_DIRTYPE_ASFINI	1
1539
#define	NVM_DIRTYPE_EXTVPD	20
1540
#define	NVM_PTREV_BCVER		0x94
1541
#define	NVM_BCVER_MAJMSK	0x0000ff00
1542
#define	NVM_BCVER_MAJSFT	8
1543
#define	NVM_BCVER_MINMSK	0x000000ff
1370 1544

  
1371 1545
/*
1372 1546
 * NVM access register
1373 1547
 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
1374 1548
 * and BCM5715 only.
1375 1549
 */
1376
#define	NVM_ACCESS_REG			0X7024
1377
#define	NVM_WRITE_ENABLE		0X00000002
1378
#define	NVM_ACCESS_ENABLE		0X00000001
1550
#define	NVM_ACCESS_REG			0x7024
1551
#define	NVM_WRITE_ENABLE		0x00000002
1552
#define	NVM_ACCESS_ENABLE		0x00000001
1379 1553

  
1380 1554
/*
1381 1555
 * TLP Control Register
......
1406 1580
/*
1407 1581
 * Vendor-specific MII registers
1408 1582
 */
1583

  
1584
#define	MII_MMD_CTRL			0x0d /* MMD Access Control register */
1585
#define	MII_MMD_CTRL_DATA_NOINC		0x4000
1586
#define	MII_MMD_ADDRESS_DATA		0x0e /* MMD Address Data register */
1587

  
1588
#define	MII_RXR_COUNTERS		0x14 /* Local/Remote Rx Counts */
1589
#define	MII_DSP_RW_PORT			0x15 /* DSP read/write port */
1590
#define	MII_DSP_CONTROL			0x16 /* DSP control register */
1591
#define	MII_DSP_ADDRESS			0x17 /* DSP address register */
1592

  
1593
#define	MII_DSP_TAP26			0x001a
1594
#define	MII_DSP_TAP26_ALNOKO		0x0001
1595
#define	MII_DSP_TAP26_RMRXSTO		0x0002
1596
#define	MII_DSP_TAP26_OPCSINPT		0x0004
1597

  
1598
#define	MII_DSP_CH34TP2			0x4022
1599
#define	MII_DSP_CH34TP2_HIBW01		0x017b
1600

  
1409 1601
#define	MII_EXT_CONTROL			MII_VENDOR(0)
1410 1602
#define	MII_EXT_STATUS			MII_VENDOR(1)
1411 1603
#define	MII_RCV_ERR_COUNT		MII_VENDOR(2)
......
1491 1683
#define	MII_AUX_CTRL_MISC_WRITE_ENABLE	0x8000
1492 1684
#define	MII_AUX_CTRL_MISC_WIRE_SPEED	0x0010
1493 1685

  
1686
#define MII_AUX_CTRL_TX_6DB		0x0400
1687
#define MII_AUX_CTRL_SMDSP_ENA		0x0800
1688

  
1494 1689
/*
1495 1690
 * Write this value to the AUX control register
1496 1691
 * to select which shadow register will be read
......
1611 1806
#define	SBD_FLAG_IP_CKSUM		0x0002
1612 1807
#define	SBD_FLAG_PACKET_END		0x0004
1613 1808
#define	SBD_FLAG_IP_FRAG		0x0008
1809
#define	SBD_FLAG_JMB_PKT		0x0008
1614 1810
#define	SBD_FLAG_IP_FRAG_END		0x0010
1615 1811

  
1616 1812
#define	SBD_FLAG_VLAN_TAG		0x0040
......
2095 2291

  
2096 2292
#endif /* BGE_IPMI_ASF */
2097 2293

  
2294
/* APE registers.  Accessible through BAR1 */
2295
#define BGE_APE_GPIO_MSG		0x0008
2296
#define BGE_APE_GPIO_MSG_SHIFT		4
2297
#define BGE_APE_EVENT			0x000c
2298
#define  APE_EVENT_1			 0x00000001
2299
#define BGE_APE_LOCK_REQ		0x002c
2300
#define  APE_LOCK_REQ_DRIVER		 0x00001000
2301
#define BGE_APE_LOCK_GRANT		0x004c
2302
#define  APE_LOCK_GRANT_DRIVER		 0x00001000
2303
#define BGE_APE_STICKY_TMR		0x00b0
2304

  
2305
/* APE shared memory.  Accessible through BAR1 */
2306
#define BGE_APE_SHMEM_BASE		0x4000
2307
#define BGE_APE_SEG_SIG			0x4000
2308
#define  APE_SEG_SIG_MAGIC		 0x41504521
2309
#define BGE_APE_FW_STATUS		0x400c
2310
#define  APE_FW_STATUS_READY		 0x00000100
2311
#define BGE_APE_FW_FEATURES		0x4010
2312
#define  BGE_APE_FW_FEATURE_NCSI	 0x00000002
2313
#define BGE_APE_FW_VERSION		0x4018
2314
#define  APE_FW_VERSION_MAJMSK		 0xff000000
2315
#define  APE_FW_VERSION_MAJSFT		 24
2316
#define  APE_FW_VERSION_MINMSK		 0x00ff0000
2317
#define  APE_FW_VERSION_MINSFT		 16
2318
#define  APE_FW_VERSION_REVMSK		 0x0000ff00
2319
#define  APE_FW_VERSION_REVSFT		 8
2320
#define  APE_FW_VERSION_BLDMSK		 0x000000ff
2321
#define BGE_APE_SEG_MSG_BUF_OFF		0x401c
2322
#define BGE_APE_SEG_MSG_BUF_LEN		0x4020
2323
#define BGE_APE_HOST_SEG_SIG		0x4200
2324
#define  APE_HOST_SEG_SIG_MAGIC		 0x484f5354
2325
#define BGE_APE_HOST_SEG_LEN		0x4204
2326
#define  APE_HOST_SEG_LEN_MAGIC		 0x00000020
2327
#define BGE_APE_HOST_INIT_COUNT		0x4208
2328
#define BGE_APE_HOST_DRIVER_ID		0x420c
2329
#define  APE_HOST_DRIVER_ID_SOLARIS	0xf4000000
2330
#define  APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2331
	(APE_HOST_DRIVER_ID_SOLARIS | (maj & 0xff) << 16 | (min & 0xff) << 8)
2332
#define BGE_APE_HOST_BEHAVIOR		0x4210
2333
#define  APE_HOST_BEHAV_NO_PHYLOCK	 0x00000001
2334
#define BGE_APE_HOST_HEARTBEAT_INT_MS	0x4214
2335
#define  APE_HOST_HEARTBEAT_INT_DISABLE	 0
2336
#define  APE_HOST_HEARTBEAT_INT_5SEC	 5000
2337
#define BGE_APE_HOST_HEARTBEAT_COUNT	0x4218
2338
#define BGE_APE_HOST_DRVR_STATE		0x421c
2339
#define BGE_APE_HOST_DRVR_STATE_START	 0x00000001
2340
#define BGE_APE_HOST_DRVR_STATE_UNLOAD	 0x00000002
2341
#define BGE_APE_HOST_DRVR_STATE_WOL	 0x00000003
2342
#define BGE_APE_HOST_WOL_SPEED		0x4224
2343
#define BGE_APE_HOST_WOL_SPEED_AUTO	 0x00008000
2344

  
2345
#define BGE_APE_EVENT_STATUS		0x4300
2346

  
2347
#define  APE_EVENT_STATUS_DRIVER_EVNT	 0x00000010
2348
#define  APE_EVENT_STATUS_STATE_CHNGE	 0x00000500
2349
#define  APE_EVENT_STATUS_SCRTCHPD_READ	 0x00001600
2350
#define  APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2351
#define  APE_EVENT_STATUS_STATE_START	 0x00010000
2352
#define  APE_EVENT_STATUS_STATE_UNLOAD	 0x00020000
2353
#define  APE_EVENT_STATUS_STATE_WOL	 0x00030000
2354
#define  APE_EVENT_STATUS_STATE_SUSPEND	 0x00040000
2355
#define  APE_EVENT_STATUS_EVENT_PENDING	 0x80000000
2356

  
2357
#define BGE_APE_PER_LOCK_REQ		0x8400
2358
#define  APE_LOCK_PER_REQ_DRIVER	 0x00001000
2359
#define BGE_APE_PER_LOCK_GRANT		0x8420
2360
#define  APE_PER_LOCK_GRANT_DRIVER	 0x00001000
2361

  
2362
/* APE convenience enumerations. */
2363
#define BGE_APE_LOCK_PHY0		0
2364
#define BGE_APE_LOCK_GRC		1
2365
#define BGE_APE_LOCK_PHY1		2
2366
#define BGE_APE_LOCK_PHY2		3
2367
#define BGE_APE_LOCK_MEM		4
2368
#define BGE_APE_LOCK_PHY3		5
2369
#define BGE_APE_LOCK_GPIO		7
2370

  
2098 2371
#ifdef __cplusplus
2099 2372
}
2100 2373
#endif
2101
-- usr/src/uts/common/io/bge/bge_kstats.c	2014-02-12 08:11:52.976562500 -0500
2374
++ usr/src/uts/common/io/bge/bge_kstats.c	2013-06-28 19:01:04.000000000 -0400
......
20 20
 */
21 21

  
22 22
/*
23
 * Copyright (c) 2010-2013, by Broadcom, Inc.
24
 * All Rights Reserved.
25
 */
26

  
27
/*
23 28
 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24 29
 * Use is subject to license terms.
25 30
 */
......
286 291
	{ 18,				"&supported"		},
287 292
	{ 19,				"&interface"		},
288 293

  
294
	{ 20,				"nvtype"		},
295

  
296
	{ 21,				"asic_rev_prod_id"	},
297

  
289 298
	{ -1,				NULL 			}
290 299
};
291 300

  
......
343 352
	bge_set_char_kstat(knp++,
344 353
	    tmp & CHIP_FLAG_SERDES ? "serdes" : "copper");
345 354

  
355
	(knp++)->value.ui64 =
356
	    ((bgep->chipid.nvtype == BGE_NVTYPE_NONE) ||
357
	     (bgep->chipid.nvtype == BGE_NVTYPE_UNKNOWN)) ?
358
	    0 : bgep->chipid.nvtype;
359

  
360
	(knp++)->value.ui64 = bgep->chipid.asic_rev_prod_id;
361

  
346 362
	return (0);
347 363
}
348 364

  
......
379 395
	{ 25,				"buff_mgr_status"	},
380 396
	{ 26,				"rcv_init_status"	},
381 397

  
398
	{ 27,				"&version"		},
399

  
382 400
	{ -1,				NULL 			}
383 401
};
384 402

  
......
448 466
	}
449 467
	mutex_exit(bgep->genlock);
450 468

  
469
	bge_set_char_kstat(knp++, bgep->version);
470

  
451 471
	return (0);
452 472
}
453 473

  
......
499 519
	{ MII_INTR_STATUS,		"intr_status"		},
500 520
	{ MII_INTR_MASK,		"intr_mask"		},
501 521
	{ MII_HCD_STATUS,		"hcd_status"		},
522
	{ EEE_MODE_REG,			"eee"			},
502 523

  
503 524
	{ -1,				NULL }
504 525
};
......
540 561
			knp->value.ui64 |= bge_mii_get16(bgep, MII_PHYIDL);
541 562
			break;
542 563

  
564
		case EEE_MODE_REG:
565
			knp->value.ui64 = 0;
566
			if (bgep->link_state == LINK_STATE_UP)
567
			{
568
				knp->value.ui64 =
569
				    (bge_reg_get32(bgep, EEE_MODE_REG) & 0x80) ?
570
				        1 : 0;
571
			}
572
			break;
573

  
543 574
		default:
544 575
			knp->value.ui64 = bge_mii_get16(bgep, ksip->index);
545 576
			break;
......
567 598

  
568 599
	size /= sizeof (bge_ksindex_t);
569 600
	ksp = kstat_create(BGE_DRIVER_NAME, instance, name, "net",
570
	    KSTAT_TYPE_NAMED, size-1, KSTAT_FLAG_PERSISTENT);
601
	    KSTAT_TYPE_NAMED, size-1, 0);
571 602
	if (ksp == NULL)
572 603
		return (NULL);
573 604

  
......
663 694
	bge_statistics_t *bstp;
664 695
	bge_statistics_reg_t *pstats;
665 696

  
666
	if (bgep->bge_chip_state == BGE_CHIP_FAULT) {
697
	if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
667 698
		return (EINVAL);
668 699
	}
669 700

  
......
735 766

  
736 767
	switch (stat) {
737 768
	case MAC_STAT_IFSPEED:
738
		*val = bgep->param_link_speed * 1000000ull;
769
		*val = (bgep->link_state != LINK_STATE_UNKNOWN) ?
770
		           (bgep->param_link_speed * 1000000ull) : 0;
739 771
		break;
740 772

  
741 773
	case MAC_STAT_MULTIRCV:
......
916 948
			*val = pstats->dot3StatsFrameTooLongs;
917 949
		break;
918 950

  
951
#if (MAC_VERSION > 1)
919 952
	case ETHER_STAT_TOOSHORT_ERRORS:
920 953
		if (bgep->chipid.statistic_type == BGE_STAT_BLK)
921 954
			*val = bstp->s.etherStatsUndersizePkts;
922 955
		else
923 956
			*val = pstats->etherStatsUndersizePkts;
924 957
		break;
958
#endif
925 959

  
926 960
	case ETHER_STAT_XCVR_ADDR:
927 961
		*val = bgep->phy_mii_addr;
......
994 1028
		*val = 1;
995 1029
		break;
996 1030

  
1031
#if (MAC_VERSION > 1)
997 1032
	case ETHER_STAT_CAP_REMFAULT:
998 1033
		*val = 1;
999 1034
		break;
1035
#endif
1000 1036

  
1001 1037
	case ETHER_STAT_ADV_CAP_1000FDX:
1002 1038
		*val = bgep->param_adv_1000fdx;
......
1034 1070
		*val = bgep->param_adv_autoneg;
1035 1071
		break;
1036 1072

  
1073
#if (MAC_VERSION > 1)
1037 1074
	case ETHER_STAT_ADV_REMFAULT:
1038 1075
		if (bgep->chipid.flags & CHIP_FLAG_SERDES)
1039 1076
			*val = 0;
......
1049 1086
			mutex_exit(bgep->genlock);
1050 1087
		}
1051 1088
		break;
1089
#endif
1052 1090

  
1053 1091
	case ETHER_STAT_LP_CAP_1000FDX:
1054 1092
		*val = bgep->param_lp_1000fdx;
......
1086 1124
		*val = bgep->param_lp_autoneg;
1087 1125
		break;
1088 1126

  
1127
#if (MAC_VERSION > 1)
1089 1128
	case ETHER_STAT_LP_REMFAULT:
1090 1129
		if (bgep->chipid.flags & CHIP_FLAG_SERDES)
1091 1130
			*val = 0;
......
1101 1140
			mutex_exit(bgep->genlock);
1102 1141
		}
1103 1142
		break;
1143
#endif
1104 1144

  
1105 1145
	case ETHER_STAT_LINK_ASMPAUSE:
1106 1146
		*val = bgep->param_adv_asym_pause &&
......
1117 1157
		break;
1118 1158

  
1119 1159
	case ETHER_STAT_LINK_DUPLEX:
1120
		*val = bgep->param_link_duplex;
1160
		*val = (bgep->link_state != LINK_STATE_UNKNOWN) ?
1161
		           bgep->param_link_duplex : LINK_DUPLEX_UNKNOWN;
1121 1162
		break;
1122 1163

  
1123 1164
	default:
1124
-- usr/src/uts/common/io/bge/bge_mii.c	2014-02-12 08:16:18.458007800 -0500
1165
++ usr/src/uts/common/io/bge/bge_mii.c	2013-06-28 19:01:04.000000000 -0400
......
20 20
 */
21 21

  
22 22
/*
23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23
 * Copyright (c) 2010-2013, by Broadcom, Inc.
24
 * All Rights Reserved.
25
 */
26

  
27
/*
28
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29
 * All rights reserved.
24 30
 */
25 31

  
26 32
#include "bge_impl.h"
......
143 149

  
144 150
#endif	/* BGE_DEBUGGING */
145 151

  
152
static void
153
bge_phy_toggle_auxctl_smdsp(bge_t *bgep,
154
                            boolean_t enable)
155
{
156
	uint16_t val;
157

  
158
	val = bge_mii_get16(bgep, MII_AUX_CONTROL);
159

  
160
	if (enable) {
161
		val |= MII_AUX_CTRL_SMDSP_ENA;
162
	} else {
163
		val &= ~MII_AUX_CTRL_SMDSP_ENA;
164
	}
165

  
166
	bge_mii_put16(bgep, MII_AUX_CONTROL, (val | MII_AUX_CTRL_TX_6DB));
167
}
168

  
146 169
/*
147 170
 * Basic low-level function to probe for a PHY
148 171
 *
......
153 176
{
154 177
	uint16_t miicfg;
155 178
	uint32_t nicsig, niccfg;
179
	int i;
156 180

  
157 181
	BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep));
158 182

  
......
174 198
		 * order to clear any sticky bits (but they should
175 199
		 * have been cleared by the RESET, I think).
176 200
		 */
177
		miicfg = bge_mii_get16(bgep, MII_STATUS);
178
		miicfg = bge_mii_get16(bgep, MII_STATUS);
201
		for (i = 0; i < 100; i++)
202
		{
203
			drv_usecwait(40);
204
			miicfg = bge_mii_get16(bgep, MII_STATUS);
205
		}
179 206
		BGE_DEBUG(("bge_phy_probe: status 0x%x", miicfg));
180 207

  
181 208
		/*
......
527 554
}
528 555

  
529 556
/*
530
 * End of Broadcom-derived workaround code				*
557
 * End of Broadcom-derived workaround code
531 558
 */
532 559

  
533 560
static int
......
536 563
	uint16_t phy_status;
537 564
	boolean_t reset_ok;
538 565
	uint16_t extctrl, auxctrl;
566
	int i;
539 567

  
540 568
	BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown));
541 569

  
542 570
	ASSERT(mutex_owned(bgep->genlock));
543 571

  
544
	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
572
	switch (MHCR_CHIP_ASIC_REV(bgep)) {
545 573
	default:
546 574
		/*
547 575
		 * Shouldn't happen; it means we don't recognise this chip.
......
559 587
	case MHCR_CHIP_ASIC_REV_5906:
560 588
	case MHCR_CHIP_ASIC_REV_5700:
561 589
	case MHCR_CHIP_ASIC_REV_5701:
562
	case MHCR_CHIP_ASIC_REV_5723:
590
	case MHCR_CHIP_ASIC_REV_5723: /* 5717 and 5725 series as well */
563 591
	case MHCR_CHIP_ASIC_REV_5721_5751:
564 592
		/*
565 593
		 * Just a plain reset; the "check" code breaks these chips
......
588 616
		break;
589 617
	}
590 618

  
591
	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
619
	switch (MHCR_CHIP_ASIC_REV(bgep)) {
592 620
	case MHCR_CHIP_ASIC_REV_5705:
593 621
	case MHCR_CHIP_ASIC_REV_5721_5751:
594 622
		bge_phy_bit_err_fix(bgep);
......
623 651
	 * order to clear any sticky bits (but they should
624 652
	 * have been cleared by the RESET, I think).
625 653
	 */
626
	phy_status = bge_mii_get16(bgep, MII_STATUS);
627
	phy_status = bge_mii_get16(bgep, MII_STATUS);
654
	for (i = 0; i < 100; i++)
655
	{
656
		drv_usecwait(40);
657
		phy_status = bge_mii_get16(bgep, MII_STATUS);
658
	}
628 659
	BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status));
629 660

  
630 661
	/*
......
635 666
	return (DDI_SUCCESS);
636 667
}
637 668

  
669
boolean_t bge_eee_cap(bge_t * bgep)
670
{
671
    if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
672
          DEVICE_5725_SERIES_CHIPSETS(bgep)))
673
    {
674
        /* EEE is not supported on this chip */
675
        BGE_DEBUG(("bge_eee: eee not supported (device 0x%x)",
676
                   bgep->chipid.device));
677
        return B_FALSE;
678
    }
679

  
680
    switch (CHIP_ASIC_REV_PROD_ID(bgep))
681
    {
682
    case CHIP_ASIC_REV_5717_B0: /* = CHIP_ASIC_REV_5718_B0 */
683
    case CHIP_ASIC_REV_5717_C0:
684
    /* case CHIP_ASIC_REV_5718_B0: */
685
    case CHIP_ASIC_REV_5719_A0:
686
    case CHIP_ASIC_REV_5719_A1:
687
    case CHIP_ASIC_REV_5720_A0:
688
    case CHIP_ASIC_REV_5725_A0:
689
    case CHIP_ASIC_REV_5727_B0:
690
        return B_TRUE;
691

  
692
    default:
693
        /* EEE is not supported on this asic rev */
694
        BGE_DEBUG(("bge_eee: eee not supported (asic rev 0x%08x)",
695
                   bgep->chipid.asic_rev));
696
        return B_FALSE;
697
    }
698
}
699

  
700
void bge_eee_init(bge_t * bgep)
701
{
702
    uint32_t val;
703

  
704
    BGE_TRACE(("bge_eee_init($%p)", (void *)bgep));
705

  
706
    ASSERT(mutex_owned(bgep->genlock));
707

  
708
    if (!bge_eee_cap(bgep))
709
    {
710
        return;
711
    }
712

  
713
    /* Enable MAC control of LPI */
714

  
715
    val = (EEE_LINK_IDLE_PCIE_NL0 | EEE_LINK_IDLE_UART_IDL);
716
    if (DEVICE_5725_SERIES_CHIPSETS(bgep))
717
        val |= EEE_LINK_IDLE_APE_TX_MT;
718
    bge_reg_put32(bgep, EEE_LINK_IDLE_CONTROL_REG, val);
719

  
720
    bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_20_1_US);
721

  
722
    val = (EEE_MODE_ERLY_L1_XIT_DET |
723
           EEE_MODE_LPI_IN_TX |
724
           EEE_MODE_LPI_IN_RX |
725
           EEE_MODE_EEE_ENABLE);
726

  
727
    if (bgep->chipid.device != DEVICE_ID_5717)
728
        val |= EEE_MODE_SND_IDX_DET_EN;
729

  
730
    //val |= EEE_MODE_APE_TX_DET_EN;
731

  
732
    if (!bgep->chipid.eee)
733
    {
734
        val = 0;
735
    }
736

  
737
    bge_reg_put32(bgep, EEE_MODE_REG, val);
738

  
739
    /* Set EEE timer debounce values */
740

  
741
    bge_reg_put32(bgep, EEE_DEBOUNCE_T1_CONTROL_REG,
742
                  (EEE_DEBOUNCE_T1_PCIEXIT_2047US |
743
                   EEE_DEBOUNCE_T1_LNKIDLE_2047US));
744

  
745
    bge_reg_put32(bgep, EEE_DEBOUNCE_T2_CONTROL_REG,
746
                  (EEE_DEBOUNCE_T2_APE_TX_2047US |
747
                   EEE_DEBOUNCE_T2_TXIDXEQ_2047US));
748
}
749

  
750
void bge_eee_autoneg(bge_t * bgep, boolean_t adv_100fdx, boolean_t adv_1000fdx)
751
{
752
    uint32_t val;
753
    uint16_t mii_val;
754

  
755
    BGE_TRACE(("bge_eee_autoneg($%p)", (void *)bgep));
756

  
757
    ASSERT(mutex_owned(bgep->genlock));
758

  
759
    if (!bge_eee_cap(bgep))
760
    {
761
        return;
762
    }
763

  
764
    /* Disable LPI Requests */
765
    val = bge_reg_get32(bgep, EEE_MODE_REG);
766
    val &= ~EEE_MODE_LPI_ENABLE;
767
    bge_reg_put32(bgep, EEE_MODE_REG, val);
768

  
769
    bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
770

  
771
    mii_val = 0;
772

  
773
    if (bgep->chipid.eee)
774
    {
775
        if (adv_100fdx)
776
        {
777
            mii_val |= EEE_CL45_D7_RESULT_STAT_LP_100TX;
778
        }
779
        if (adv_1000fdx)
780
        {
781
            mii_val |= EEE_CL45_D7_RESULT_STAT_LP_1000T;
782
        }
783
    }
784

  
785
    /* Enable EEE advertisement for the specified mode(s)... */
786
    bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
787
    bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, MDIO_AN_EEE_ADV);
788
    bge_mii_put16(bgep, MII_MMD_CTRL, MII_MMD_CTRL_DATA_NOINC | MDIO_MMD_AN);
789
    bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, mii_val);
790

  
791
    /* Setup PHY DSP for EEE */
792
    switch (bgep->chipid.device)
793
    {
794
    case DEVICE_ID_5717:
795
    case DEVICE_ID_5718:
796
    case DEVICE_ID_5719:
797
        /* If we advertised any EEE advertisements above... */
798
        if (mii_val)
799
        {
800
            mii_val = (MII_DSP_TAP26_ALNOKO |
801
                       MII_DSP_TAP26_RMRXSTO |
802
                       MII_DSP_TAP26_OPCSINPT);
803
        }
804
        bge_phydsp_write(bgep, MII_DSP_TAP26, mii_val);
805
        /* fall through */
806
    case DEVICE_ID_5720:
807
    case DEVICE_ID_5725:
808
    case DEVICE_ID_5727:
809
        mii_val = bge_phydsp_read(bgep, MII_DSP_CH34TP2);
810
        bge_phydsp_write(bgep, MII_DSP_CH34TP2,
811
                         (mii_val | MII_DSP_CH34TP2_HIBW01));
812
    }
813

  
814
    bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
815
}
816

  
817
void bge_eee_adjust(bge_t * bgep)
818
{
819
    uint32_t val;
820
    uint16_t mii_val;
821

  
822
    BGE_TRACE(("bge_eee_adjust($%p, %d)", (void *)bgep));
823

  
824
    ASSERT(mutex_owned(bgep->genlock));
825

  
826
    if (!bge_eee_cap(bgep))
827
    {
828
        return;
829
    }
830

  
831
    bgep->eee_lpi_wait = 0;
832

  
833
    /* Check for PHY link status */
834
    if (bgep->param_link_up)
835
    {
836
        BGE_DEBUG(("bge_eee_adjust: link status up"));
837

  
838
        /* XXX if duplex full and speed is 1000 or 100 then do following... */
839

  
840
        if (bgep->param_link_speed == 1000)
841
        {
842
            BGE_DEBUG(("bge_eee_adjust: eee timing for 1000Mb"));
843
            bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_16_5_US);
844
        }
845
        else if (bgep->param_link_speed == 100)
846
        {
847
            BGE_DEBUG(("bge_eee_adjust: eee timing for 100Mb"));
848
            bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_36_US);
849
        }
850

  
851
        /* Read PHY's EEE negotiation status */
852
        bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
853
        bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, EEE_CL45_D7_RESULT_STAT);
854
        bge_mii_put16(bgep, MII_MMD_CTRL, MII_MMD_CTRL_DATA_NOINC | MDIO_MMD_AN);
855
        mii_val = bge_mii_get16(bgep, MII_MMD_ADDRESS_DATA);
856

  
857
        /* Enable EEE LPI request if EEE negotiated */
858
        if ((mii_val == EEE_CL45_D7_RESULT_STAT_LP_1000T) ||
859
            (mii_val == EEE_CL45_D7_RESULT_STAT_LP_100TX))
860
        {
861
            BGE_DEBUG(("bge_eee_adjust: eee negotiaton success, lpi scheduled"));
862
            bgep->eee_lpi_wait = 2;
863
        }
864
        else
865
        {
866
            BGE_DEBUG(("bge_eee_adjust: eee negotiation failed"));
867
        }
868
    }
869
    else
870
    {
871
        BGE_DEBUG(("bge_eee_adjust: link status down"));
872
    }
873

  
874
    if (!bgep->eee_lpi_wait)
875
    {
876
        if (bgep->param_link_up)
877
        {
878
            bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
879
            bge_phydsp_write(bgep, MII_DSP_TAP26, 0);
880
            bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
881
        }
882

  
883
        /* Disable LPI requests */
884
        val = bge_reg_get32(bgep, EEE_MODE_REG);
885
        val &= ~EEE_MODE_LPI_ENABLE;
886
        bge_reg_put32(bgep, EEE_MODE_REG, val);
887
    }
888
}
889

  
890
void bge_eee_enable(bge_t * bgep)
891
{
892
    uint32_t val;
893

  
894
    /* XXX check for EEE for 5717 family... */
895

  
896
    if (bgep->param_link_speed == 1000)
897
    {
898
        bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
899
        bge_phydsp_write(bgep, MII_DSP_TAP26, (MII_DSP_TAP26_ALNOKO |
900
                                               MII_DSP_TAP26_RMRXSTO));
901
        bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
902
    }
903

  
904
    val = bge_reg_get32(bgep, EEE_MODE_REG);
905
    val |= EEE_MODE_LPI_ENABLE;
906
    bge_reg_put32(bgep, EEE_MODE_REG, val);
907
}
908

  
638 909
/*
639 910
 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities
640 911
 * and advertisements with the required settings as specified by the various
......
866 1137
		break;
867 1138
	}
868 1139
#endif	/* BGE_COPPER_WIRESPEED */
1140

  
1141
	/* enable EEE on those chips that support it */
1142
	bge_eee_autoneg(bgep, adv_100fdx, adv_1000fdx);
1143

  
869 1144
	return (DDI_SUCCESS);
870 1145
}
871 1146

  
......
877 1152
	uint16_t aux;
878 1153
	uint_t mode;
879 1154
	boolean_t linkup;
1155
	int i;
880 1156

  
881 1157
	/*
882 1158
	 * Step 10: read the status from the PHY (which is self-clearing
883 1159
	 * on read!); also read & clear the main (Ethernet) MAC status
884 1160
	 * (the relevant bits of this are write-one-to-clear).
885 1161
	 */
886
	mii_status = bge_mii_get16(bgep, MII_STATUS);
1162
	for (i = 0; i < 100; i++)
1163
	{
1164
		drv_usecwait(40);
1165
		mii_status = bge_mii_get16(bgep, MII_STATUS);
1166
	}
887 1167
	emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
888 1168
	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status);
889 1169

  
......
898 1178
	 * known), there's nothing to do.
899 1179
	 */
900 1180
	if (mii_status == bgep->phy_gen_status && !recheck)
1181
	{
1182
		BGE_DEBUG(("bge_check_copper: no link change"));
901 1183
		return (B_FALSE);
1184
	}
902 1185

  
903 1186
	do {
904 1187
		/*
905 1188
		 * Step 11: read AUX STATUS register to find speed/duplex
906 1189
		 */
907
		aux = bge_mii_get16(bgep, MII_AUX_STATUS);
1190
		for (i = 0; i < 2000; i++)
1191
		{
1192
			drv_usecwait(10);
1193
			aux = bge_mii_get16(bgep, MII_AUX_STATUS);
1194
		}
908 1195
		BGE_CDB(bge_phydump, (bgep, mii_status, aux));
909 1196

  
910 1197
		/*
......
935 1222
		 */
936 1223
		bgep->phy_aux_status = aux;
937 1224
		bgep->phy_gen_status = mii_status;
938
		mii_status = bge_mii_get16(bgep, MII_STATUS);
1225

  
1226
		for (i = 0; i < 100; i++)
1227
		{
1228
			drv_usecwait(40);
1229
			mii_status = bge_mii_get16(bgep, MII_STATUS);
1230
		}
939 1231
	} while (mii_status != bgep->phy_gen_status);
940 1232

  
941 1233
	/*
......
1014 1306
		bgep->param_link_duplex = bge_copper_link_duplex[mode];
1015 1307
	}
1016 1308

  
1017
	BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d",
1018
	    UPORDOWN(bgep->param_link_up),
1019
	    bgep->param_link_speed,
1020
	    bgep->param_link_duplex));
1309
	bge_eee_adjust(bgep);
1310

  
1311
	bge_log(bgep, "bge_check_copper: link now %s speed %d duplex %d",
1312
	        UPORDOWN(bgep->param_link_up),
1313
	        bgep->param_link_speed,
1314
	        bgep->param_link_duplex);
1021 1315

  
1022 1316
	return (B_TRUE);
1023 1317
}
......
1054 1348
	 * appropriately for the SerDes interface ...
1055 1349
	 */
1056 1350
	macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
1057
	if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1058
		macmode |= ETHERNET_MODE_LINK_POLARITY;
1059
		macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
1351
	macmode &= ~ETHERNET_MODE_LINK_POLARITY;
1352
	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
1353
	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1354
	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1355
	    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1060 1356
		macmode |= ETHERNET_MODE_PORTMODE_GMII;
1061 1357
	} else {
1062
		macmode &= ~ETHERNET_MODE_LINK_POLARITY;
1063
		macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
1064 1358
		macmode |= ETHERNET_MODE_PORTMODE_TBI;
1065 1359
	}
1066 1360
	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
......
1288 1582
		 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752,
1289 1583
		 * BCM5714, and BCM5715 devices.
1290 1584
		 */
1291
		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1585
		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1586
		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1587
		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1292 1588
			tx_status = bge_reg_get32(bgep,
1293 1589
			    TRANSMIT_MAC_STATUS_REG);
1294 1590
			linkup = BIS(tx_status, TRANSMIT_STATUS_LINK_UP);
1295 1591
			emac_status = bge_reg_get32(bgep,
1296 1592
			    ETHERNET_MAC_STATUS_REG);
1297 1593
			bgep->serdes_status = emac_status;
1594
			/* clear write-one-to-clear bits in MAC status */
1595
			if ((emac_status & ETHERNET_STATUS_MI_COMPLETE) &&
1596
			    (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1597
			     DEVICE_5725_SERIES_CHIPSETS(bgep))) {
1598
			    emac_status |= (ETHERNET_STATUS_SYNC_CHANGED |
1599
			                    ETHERNET_STATUS_CFG_CHANGED);
1600
			}
1601
			bge_reg_put32(bgep,
1602
			    ETHERNET_MAC_STATUS_REG, emac_status);
1603
			/*
1604
			 * If the link status has not changed then then
1605
			 * break. If it has loop around and recheck again.
1606
			 * Keep looping until the link status has not
1607
			 * changed.
1608
			 */
1298 1609
			if ((linkup && linkup_old) ||
1299 1610
			    (!linkup && !linkup_old)) {
1300
				emac_status &= ~ETHERNET_STATUS_LINK_CHANGED;
1301
				emac_status &= ~ETHERNET_STATUS_RECEIVING_CFG;
1302 1611
				break;
1303 1612
			}
1304
			emac_status |= ETHERNET_STATUS_LINK_CHANGED;
1305
			emac_status |= ETHERNET_STATUS_RECEIVING_CFG;
1306 1613
			if (linkup)
1307 1614
				linkup_old = B_TRUE;
1308 1615
			else
......
1467 1774
	}
1468 1775
	bgep->link_state = LINK_STATE_UNKNOWN;
1469 1776

  
1470
	BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d",
1471
	    UPORDOWN(bgep->param_link_up),
1472
	    bgep->param_link_speed,
1473
	    bgep->param_link_duplex));
1777
	bge_log(bgep, "bge_check_serdes: link now %s speed %d duplex %d",
1778
	        UPORDOWN(bgep->param_link_up),
1779
	        bgep->param_link_speed,
1780
	        bgep->param_link_duplex);
1474 1781

  
1475 1782
	return (B_TRUE);
1476 1783
}
......
1495 1802
int
1496 1803
bge_phys_init(bge_t *bgep)
1497 1804
{
1805
	uint32_t regval;
1806

  
1498 1807
	BGE_TRACE(("bge_phys_init($%p)", (void *)bgep));
1499 1808

  
1500 1809
	mutex_enter(bgep->genlock);
......
1506 1815
	 * BCM800x PHY.
1507 1816
	 */
1508 1817
	bgep->phy_mii_addr = 1;
1818

  
1509 1819
	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1510
		int regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
1511
		if (regval & CPMU_STATUS_FUN_NUM)
1512
			bgep->phy_mii_addr += 1;
1820
		bgep->phy_mii_addr = (bgep->pci_func + 1);
1513 1821
		regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
1514 1822
		if (regval & MEDIA_SELECTION_MODE)
1515
			bgep->phy_mii_addr += 7;
1823
			bgep->phy_mii_addr += 7; /* sgmii */
1516 1824
	}
1517 1825

  
1518 1826
	if (bge_phy_probe(bgep)) {
......
1606 1914
boolean_t
1607 1915
bge_phys_check(bge_t *bgep)
1608 1916
{
1609
	int32_t orig_state;
1610
	boolean_t recheck;
1611

  
1612 1917
	BGE_TRACE(("bge_phys_check($%p)", (void *)bgep));
1613 1918

  
1614 1919
	ASSERT(mutex_owned(bgep->genlock));
1615 1920

  
1616
	orig_state = bgep->link_state;
1617
	recheck = orig_state == LINK_STATE_UNKNOWN;
1618
	recheck = (*bgep->physops->phys_check)(bgep, recheck);
1619
	if (!recheck)
1620
		return (B_FALSE);
1621

  
1622
	return (B_TRUE);
1921
	/*
1922
	 * Force a link recheck if current state is unknown.
1923
	 * phys_check() returns TRUE if the link status changed, FALSE otherwise.
1924
	 */
1925
	return (*bgep->physops->phys_check)(bgep, (bgep->link_state ==
1926
	                                           LINK_STATE_UNKNOWN));
1623 1927
}
1928

  
1624
-- usr/src/uts/common/io/bge/bge_send.c	2014-02-11 23:08:30.374023400 -0500
1929
++ usr/src/uts/common/io/bge/bge_send.c	2013-06-28 19:01:04.000000000 -0400
......
20 20
 */
21 21

  
22 22
/*
23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23
 * Copyright (c) 2010-2013, by Broadcom, Inc.
24
 * All Rights Reserved.
25
 */
26

  
27
/*
28
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29
 * All rights reserved.
24 30
 */
25 31

  
26 32
#include "bge_impl.h"
......
443 449
			hw_sbd_p->flags |= SBD_FLAG_IP_CKSUM;
444 450
		if (pktp->pflags & HCK_FULLCKSUM)
445 451
			hw_sbd_p->flags |= SBD_FLAG_TCP_UDP_CKSUM;
452
		if (!(bgep->chipid.flags & CHIP_FLAG_NO_JUMBO) &&
453
		    (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
454
		     DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
455
		    (txbuf->copy_len > ETHERMAX))
456
			hw_sbd_p->flags |= SBD_FLAG_JMB_PKT;
446 457
		hw_sbd_p->flags |= SBD_FLAG_PACKET_END;
447 458

  
448 459
		txfill_next = NEXT(txfill_next, BGE_SEND_BUF_MAX);
449
-- usr/src/uts/common/io/bge/bge_chip2.c	2014-02-12 08:11:23.231445300 -0500
460
++ usr/src/uts/common/io/bge/bge_chip2.c	2014-02-13 18:48:57.482421800 -0500
......
20 20
 */
21 21

  
22 22
/*
23
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23
 * Copyright (c) 2010-2013, by Broadcom, Inc.
24
 * All Rights Reserved.
24 25
 */
25 26

  
26 27
/*
27
 * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
28
 * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29
 * All rights reserved.
28 30
 */
29 31

  
30 32
#include "bge_impl.h"
31 33

  
32 34
#define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
35
#define	APE_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->ape_regs+(offset)))
33 36

  
34 37
/*
35 38
 * Future features ... ?
......
54 57
boolean_t bge_relaxed_ordering = B_TRUE;
55 58

  
56 59
/*
57
 * Property names
58
 */
59
static char knownids_propname[] = "bge-known-subsystems";
60

  
61
/*
62 60
 * Patchable globals:
63 61
 *
64 62
 *	bge_autorecover
......
98 96
static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
99 97

  
100 98
uint32_t bge_rx_ticks_norm = 128;
101
uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
99
uint32_t bge_tx_ticks_norm = 512;
102 100
uint32_t bge_rx_count_norm = 8;
103 101
uint32_t bge_tx_count_norm = 128;
104 102

  
......
243 241
	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
244 242

  
245 243
#ifdef __sparc
246
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
244
	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
245
	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
247 246
		regno = LE_32(regno);
247
	}
248 248
#endif
249 249
	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
250 250
	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
......
268 268

  
269 269
	val = LE_32(val);
270 270
#ifdef __sparc
271
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
271
	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
272
	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
272 273
		regno = LE_32(regno);
274
	}
273 275
#endif
274 276
	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
275 277
	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
......
327 329
	ddi_acc_handle_t handle;
328 330
	uint16_t command;
329 331
	uint32_t mhcr;
332
	uint32_t prodid;
333
	uint32_t pci_state;
330 334
	uint16_t value16;
331 335
	int i;
332 336

  
......
360 364
	 * byte-swapped value to it. So we just write zero first for simplicity.
361 365
	 */
362 366
	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
363
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
367
	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
368
	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
364 369
		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
370
	}
371

  
365 372
	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
366
	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
373
	cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK);
374
	cidp->asic_rev_prod_id = 0;
375
	if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) {
376
		prodid = CHIP_ASIC_REV_PROD_ID_REG;
377
		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
378
		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
379
			prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG;
380
		}
381
		cidp->asic_rev_prod_id = pci_config_get32(handle, prodid);
382
	}
383

  
367 384
	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
368 385
	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
369 386

  
......
374 391
	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
375 392
	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
376 393

  
394
	/* 5717 C0 is treated just like 5720 A0 */
395
	if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
396
	    DEVICE_ID_5717_C0) {
397
		cidp->device = DEVICE_ID_5720;
398
	}
399

  
377 400
	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
378 401
	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
379 402
	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
......
445 468
	 * see whether the host is truly up to date, and regenerate
446 469
	 * its interrupt if not.
447 470
	 */
448
	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
449
	    MHCR_ENABLE_TAGGED_STATUS_MODE |
450
	    MHCR_MASK_INTERRUPT_MODE |
451
	    MHCR_CLEAR_INTERRUPT_INTA;
452

  
471
	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
472
	       MHCR_ENABLE_PCI_STATE_RW |
473
	       MHCR_ENABLE_TAGGED_STATUS_MODE |
474
	       MHCR_MASK_INTERRUPT_MODE |
475
	       MHCR_CLEAR_INTERRUPT_INTA;
453 476
	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
454 477
		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
455 478

  
456 479
#ifdef	_BIG_ENDIAN
457 480
	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
458 481
#endif	/* _BIG_ENDIAN */
459

  
460
	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
461
		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
462 482
	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
463 483

  
464 484
#ifdef BGE_IPMI_ASF
465 485
	bgep->asf_wordswapped = B_FALSE;
466 486
#endif
487

  
488
	pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY);
489
	/* allow reads and writes to the APE register and memory space */
490
	if (bgep->ape_enabled) {
491
		pci_state |= (PCISTATE_ALLOW_APE_CTLSPC_WR |
492
		              PCISTATE_ALLOW_APE_SHMEM_WR |
493
		              PCISTATE_ALLOW_APE_PSPACE_WR);
494
	}
495
	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state);
496

  
467 497
	/*
468 498
	 * Step 1 (also step 7): Enable PCI Memory Space accesses
469 499
	 *			 Disable Memory Write/Invalidate
......
533 563
		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
534 564
			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
535 565
			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
536
		} else
566
		} else if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
567
		           DEVICE_5725_SERIES_CHIPSETS(bgep)) {
568
			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
569
			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
570
		} else {
537 571
			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
538 572
			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
573
		}
539 574
	}
540 575
}
541 576

  
......
629 664
	uint64_t regval;
630 665

  
631 666
#ifdef	__amd64
632
	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
633
	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
667
	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
... This diff was truncated because it exceeds the maximum size that can be displayed.
(10-10/10)