bge_illumos_kmays_021414-01.patch - illumos gate - illumos

Feature #3446 » bge_illumos_kmays_021414-01.patch

Ken Mays, 2014-02-14 01:01 AM

      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
      * Copyright (c) 2010-2013, by Broadcom, Inc.
      * All Rights Reserved.
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
      * All rights reserved.
      */
     #ifndef _BGE_HW_H
-...
     #define	DEVICE_ID_5705C			0x1653
     #define	DEVICE_ID_5705_2		0x1654
     #define	DEVICE_ID_5717			0x1655
     #define	DEVICE_ID_5717_C0		0x1665
     #define	DEVICE_ID_5718			0x1656
     #define	DEVICE_ID_5719			0x1657
     #define	DEVICE_ID_5720			0x165f
     #define	DEVICE_ID_5724			0x165c
     #define	DEVICE_ID_5725			0x1643
     #define	DEVICE_ID_5727			0x16f3
     #define	DEVICE_ID_5705M			0x165d
     #define	DEVICE_ID_5705MA3		0x165e
     #define	DEVICE_ID_5705F			0x166e
-...
     		(bgep->chipid.device == DEVICE_ID_5789))
     #define	DEVICE_5717_SERIES_CHIPSETS(bgep) \
     		(bgep->chipid.device == DEVICE_ID_5717) ||\
     		((bgep->chipid.device == DEVICE_ID_5717) ||\
     		(bgep->chipid.device == DEVICE_ID_5718) ||\
     		(bgep->chipid.device == DEVICE_ID_5724)
     		(bgep->chipid.device == DEVICE_ID_5719) ||\
     		(bgep->chipid.device == DEVICE_ID_5720) ||\
     		(bgep->chipid.device == DEVICE_ID_5724))
     #define	DEVICE_5725_SERIES_CHIPSETS(bgep) \
     		((bgep->chipid.device == DEVICE_ID_5725) ||\
     		(bgep->chipid.device == DEVICE_ID_5727))
     #define	DEVICE_5723_SERIES_CHIPSETS(bgep) \
     		((bgep->chipid.device == DEVICE_ID_5723) ||\
-...
     #define	MHCR_ENABLE_INDIRECT_ACCESS	0x00000080
     #define	MHCR_ENABLE_REGISTER_WORD_SWAP	0x00000040
     #define	MHCR_ENABLE_CLOCK_CONTROL_WRITE	0x00000020
     #define	MHCR_ENABLE_PCI_STATE_WRITE	0x00000010
     #define	MHCR_ENABLE_PCI_STATE_RW	0x00000010
     #define	MHCR_ENABLE_ENDIAN_WORD_SWAP	0x00000008
     #define	MHCR_ENABLE_ENDIAN_BYTE_SWAP	0x00000004
     #define	MHCR_MASK_PCI_INT_OUTPUT	0x00000002
     #define	MHCR_CLEAR_INTERRUPT_INTA	0x00000001
     #define	MHCR_BOUNDARY_CHECK		0x00002000
     #define	MHCR_TLP_MINOR_ERR_TOLERANCE	0x00008000
     #define	MHCR_CHIP_REV_5700_B0		0x71000000
     #define	MHCR_CHIP_REV_5700_B2		0x71020000
-...
     #define	MHCR_CHIP_REV_5906_A1		0xc0010000
     #define	MHCR_CHIP_REV_5906_A2		0xc0020000
     #define	MHCR_CHIP_REV_5723_A0		0xf0000000
     #define	MHCR_CHIP_REV_5723_A1		0xf0010000
     #define	MHCR_CHIP_REV_5723_A2		0xf0020000
     #define	MHCR_CHIP_REV_5723_B0		0xf1000000
     #define	CHIP_ASIC_REV_USE_PROD_ID_REG	0xf0000000
     #define MHCR_CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev & 0xf0000000)
     #define CHIP_ASIC_REV_PROD_ID(bgep) ((bgep)->chipid.asic_rev_prod_id)
     #define CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev_prod_id >> 12)
     #define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) & 0xf0000000)
     #define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
     #define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
     #define	MHCR_CHIP_ASIC_REV_5703		(0x1 << 28)
-...
     #define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
     #define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
     #define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
     /* (0xf << 28) touches all 5717 and 5725 series as well (OK) */
     #define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
     #define	CHIP_ASIC_REV_5723		0x5784
     #define	CHIP_ASIC_REV_5761		0x5761
     #define	CHIP_ASIC_REV_5785		0x5785
     #define	CHIP_ASIC_REV_57780		0x57780
     #define	CHIP_ASIC_REV_5717		0x5717
     #define	CHIP_ASIC_REV_5719		0x5719
     #define	CHIP_ASIC_REV_5720		0x5720
     #define	CHIP_ASIC_REV_5762		0x5762 /* 5725/5727 */
     #define	CHIP_ASIC_REV_PROD_ID_REG	0x000000bc
     #define	CHIP_ASIC_REV_PROD_ID_GEN2_REG	0x000000f4
     #define	CHIP_ASIC_REV_5717_B0		0x05717100
     #define	CHIP_ASIC_REV_5717_C0		0x05717200
     #define	CHIP_ASIC_REV_5718_B0		0x05717100
     #define	CHIP_ASIC_REV_5719_A0		0x05719000
     #define	CHIP_ASIC_REV_5719_A1		0x05719001
     #define	CHIP_ASIC_REV_5720_A0		0x05720000
     #define	CHIP_ASIC_REV_5725_A0		0x05762000
     #define	CHIP_ASIC_REV_5727_B0		0x05762100
     /*
      * PCI DMA read/write Control Register, in PCI config space
-...
      * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
      */
     #define	PCI_CONF_BGE_PCISTATE		0x70
     #define	PCISTATE_ALLOW_APE_CTLSPC_WR	0x00010000
     #define	PCISTATE_ALLOW_APE_SHMEM_WR	0x00020000
     #define	PCISTATE_ALLOW_APE_PSPACE_WR	0x00040000
     #define	PCISTATE_RETRY_SAME_DMA		0x00002000
     #define	PCISTATE_FLAT_VIEW		0x00000100
     #define	PCISTATE_EXT_ROM_RETRY		0x00000040
-...
      */
     #define	PCI_CONF_DEV_CTRL		0xd8
     #define	PCI_CONF_DEV_CTRL_5723		0xd4
     #define	PCI_CONF_DEV_CTRL_5717		0xb4
     #define	READ_REQ_SIZE_MASK		0x7000
     #define	READ_REQ_SIZE_MAX		0x5000
     #define	READ_REQ_SIZE_2K 		0x4000
     #define	DEV_CTRL_NO_SNOOP		0x0800
     #define	DEV_CTRL_RELAXED		0x0010
-...
     #define	NIC_MEM_SHADOW_SEND_7_8		0x7000		/* bogus	*/
     #define	NIC_MEM_SHADOW_SEND_9_16	0x8000		/* bogus	*/
     #define	NIC_MEM_SHADOW_BUFF_STD		0x6000
     #define	NIC_MEM_SHADOW_BUFF_STD_5717		0x40000
     #define	NIC_MEM_SHADOW_BUFF_STD_5717	0x40000
     #define	NIC_MEM_SHADOW_BUFF_JUMBO	0x7000
     #define	NIC_MEM_SHADOW_BUFF_MINI	0x8000		/* bogus	*/
     #define	NIC_MEM_SHADOW_SEND_RING(ring, nslots)	(0x4000 + 4*(ring)*(nslots))
-...
     #define	HOST_COALESCE_MODE_REG		0x3c00
     #define	MEMORY_ARBITER_MODE_REG		0x4000
     #define	BUFFER_MANAGER_MODE_REG		0x4400
     #define	BUFFER_MANAGER_MODE_NO_TX_UNDERRUN	0x80000000
     #define	BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE	0x00000010
     #define	READ_DMA_MODE_REG		0x4800
     #define	WRITE_DMA_MODE_REG		0x4c00
     #define	DMA_COMPLETION_MODE_REG		0x6400
     #define	FAST_BOOT_PC			0x6894
     #define	RDMA_RSRV_CTRL_REG		0x4900
     #define	RDMA_RSRV_CTRL_REG2		0x4890
     #define	RDMA_RSRV_CTRL_FIFO_OFLW_FIX	0x00000004
     #define	RDMA_RSRV_CTRL_FIFO_LWM_1_5K	0x00000c00
     #define	RDMA_RSRV_CTRL_FIFO_LWM_MASK	0x00000ff0
     #define	RDMA_RSRV_CTRL_FIFO_HWM_1_5K	0x000c0000
     #define	RDMA_RSRV_CTRL_FIFO_HWM_MASK	0x000ff000
     #define	RDMA_RSRV_CTRL_TXMRGN_320B	0x28000000
     #define	RDMA_RSRV_CTRL_TXMRGN_MASK	0xffe00000
     #define	RDMA_CORR_CTRL_REG		0x4910
     #define	RDMA_CORR_CTRL_REG2		0x48a0
     #define	RDMA_CORR_CTRL_BLEN_BD_4K	0x00030000
     #define	RDMA_CORR_CTRL_BLEN_LSO_4K	0x000c0000
     #define RDMA_CORR_CTRL_TX_LENGTH_WA	0x02000000
     #define BGE_NUM_RDMA_CHANNELS		4
     #define BGE_RDMA_LENGTH			0x4be0
     /*
      * Other bits in some of the above state machine control registers
-...
      * Transmit MAC Mode Register
      * (TRANSMIT_MAC_MODE_REG, 0x045c)
      */
     #define	TRANSMIT_MODE_MBUF_LOCKUP_FIX	0x00000100
     #define	TRANSMIT_MODE_LONG_PAUSE	0x00000040
     #define	TRANSMIT_MODE_BIG_BACKOFF	0x00000020
     #define	TRANSMIT_MODE_FLOW_CONTROL	0x00000010
-...
      * Ethernet MAC Mode Register
      */
     #define	ETHERNET_MAC_MODE_REG		0x0400
     #define	ETHERNET_MODE_APE_TX_EN		0x10000000
     #define	ETHERNET_MODE_APE_RX_EN		0x08000000
     #define	ETHERNET_MODE_ENABLE_FHDE	0x00800000
     #define	ETHERNET_MODE_ENABLE_RDE	0x00400000
     #define	ETHERNET_MODE_ENABLE_TDE	0x00200000
-...
     #define	SERDES_STATUS_COMMA_DETECTED	0x00000100
     #define	SERDES_STATUS_RXSTAT		0x000000ff
     /* 5780/5714 only */
     #define SERDES_RX_CONTROL		0x000005b0
     #define SERDES_RX_CONTROL_SIG_DETECT	0x00000400
     /*
      * SGMII Status Register (5717/5718 only)
      * SGMII Status Register (5717/18/19/20 only)
      */
     #define	SGMII_STATUS_REG	0x5B4
     #define	MEDIA_SELECTION_MODE	0x00000100
-...
     #define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
     /*
      * CPMU registers (5717/5718 only)
      * CPMU registers (5717/18/19/20 only)
      */
     #define	CPMU_STATUS_REG	0x362c
     #define	CPMU_STATUS_FUN_NUM	0x20000000
     #define	CPMU_CLCK_ORIDE_REG		0x3624
     #define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
     #define	CPMU_STATUS_REG			0x362c
     #define	CPMU_STATUS_FUNC_NUM		0x20000000
     #define	CPMU_STATUS_FUNC_NUM_SHIFT	29
     #define	CPMU_STATUS_FUNC_NUM_5719 	0xc0000000
     #define	CPMU_STATUS_FUNC_NUM_5719_SHIFT	30
     /*
      * EEE registers (5718/19/20 only)
      */
     #define	EEE_MODE_REG			0x36b0
     #define	EEE_MODE_APE_TX_DET_EN		0x00000004
     #define	EEE_MODE_ERLY_L1_XIT_DET	0x00000008
     #define	EEE_MODE_SND_IDX_DET_EN		0x00000040
     #define	EEE_MODE_LPI_ENABLE		0x00000080
     #define	EEE_MODE_LPI_IN_TX		0x00000100
     #define	EEE_MODE_LPI_IN_RX		0x00000200
     #define	EEE_MODE_EEE_ENABLE		0x00100000
     #define	EEE_DEBOUNCE_T1_CONTROL_REG	0x36b4
     #define	EEE_DEBOUNCE_T1_PCIEXIT_2047US	0x07ff0000
     #define	EEE_DEBOUNCE_T1_LNKIDLE_2047US	0x000007ff
     #define	EEE_DEBOUNCE_T2_CONTROL_REG	0x36b8
     #define	EEE_DEBOUNCE_T2_APE_TX_2047US	0x07ff0000
     #define	EEE_DEBOUNCE_T2_TXIDXEQ_2047US	0x000007ff
     #define	EEE_LINK_IDLE_CONTROL_REG	0x36bc
     #define	EEE_LINK_IDLE_PCIE_NL0		0x01000000
     #define	EEE_LINK_IDLE_UART_IDL		0x00000004
     #define	EEE_LINK_IDLE_APE_TX_MT		0x00000002
     #define	EEE_CONTROL_REG			0x36d0
     #define	EEE_CONTROL_EXIT_16_5_US	0x0000019d
     #define	EEE_CONTROL_EXIT_36_US		0x00000384
     #define	EEE_CONTROL_EXIT_20_1_US	0x000001f8
     /* Clause 45 expansion registers */
     #define	EEE_CL45_D7_RESULT_STAT			0x803e
     #define	EEE_CL45_D7_RESULT_STAT_LP_100TX	0x0002
     #define	EEE_CL45_D7_RESULT_STAT_LP_1000T	0x0004
     #define MDIO_MMD_AN			0x0007
     #define MDIO_AN_EEE_ADV			0x003c
     /*
      * Host Coalescing Engine Control Registers
-...
      * Miscellaneous Local Control Register (MLCR)
      */
     #define	MISC_LOCAL_CONTROL_REG		0x6808
     #define	MLCR_PCI_CTRL_SELECT		0x10000000
     #define	MLCR_LEGACY_PCI_MODE		0x08000000
     #define	MLCR_AUTO_SEEPROM_ACCESS	0x01000000
     #define	MLCR_SSRAM_CYCLE_DESELECT	0x00800000
     #define	MLCR_SSRAM_TYPE			0x00400000
     #define	MLCR_BANK_SELECT		0x00200000
     #define	MLCR_SRAM_SIZE_16M		0x00180000
     #define	MLCR_SRAM_SIZE_8M		0x00140000
     #define	MLCR_SRAM_SIZE_4M		0x00100000
     #define	MLCR_SRAM_SIZE_2M		0x000c0000
     #define	MLCR_SRAM_SIZE_1M		0x00080000
     #define	MLCR_SRAM_SIZE_512K		0x00040000
     #define	MLCR_SRAM_SIZE_256K		0x00000000
     #define	MLCR_SRAM_SIZE_MASK		0x001c0000
     #define	MLCR_ENABLE_EXTERNAL_MEMORY	0x00020000
     #define	MLCR_ENABLE_EXTERNAL_MEMORY	0x00020000
     #define	MLCR_MISC_PINS_OUTPUT_2		0x00010000
     #define	MLCR_MISC_PINS_OUTPUT_1		0x00008000
     #define	MLCR_MISC_PINS_OUTPUT_0		0x00004000
     #define	MLCR_MISC_PINS_OUTPUT_ENABLE_2	0x00002000
     #define	MLCR_MISC_PINS_OUTPUT_ENABLE_1	0x00001000
     #define	MLCR_MISC_PINS_OUTPUT_ENABLE_0	0x00000800
     #define	MLCR_MISC_PINS_INPUT_2		0x00000400	/* R/O	*/
     #define	MLCR_MISC_PINS_INPUT_1		0x00000200	/* R/O	*/
     #define	MLCR_MISC_PINS_INPUT_0		0x00000100	/* R/O	*/
     #define	MLCR_GPIO_OUTPUT3		0x00000080
     #define	MLCR_GPIO_OE3			0x00000040
     #define	MLCR_USE_EXT_SIG_DETECT		0x00000020	/* 5714/5780 only */
     #define	MLCR_GPIO_INPUT3		0x00000020
     #define	MLCR_GPIO_UART_SEL		0x00000010	/* 5755 only */
     #define	MLCR_USE_SIG_DETECT		0x00000010	/* 5714/5780 only */
     #define	MLCR_INT_ON_ATTN		0x00000008	/* R/W	*/
     #define	MLCR_SET_INT			0x00000004	/* W/O	*/
     #define	MLCR_CLR_INT			0x00000002	/* W/O	*/
-...
      * just this fashion.  It has to be set as an OUTPUT and driven LOW to
      * enable writing.  Otherwise, the SEEPROM is protected.
      */
     #define	MLCR_DEFAULT			0x0101c000
     #define	MLCR_DEFAULT_5714		0x1901c000
     #define	MLCR_DEFAULT_5717		0x01000000
     #define	MLCR_DEFAULT			(MLCR_AUTO_SEEPROM_ACCESS | \
     					 MLCR_MISC_PINS_OUTPUT_2  | \
     					 MLCR_MISC_PINS_OUTPUT_1  | \
     					 MLCR_MISC_PINS_OUTPUT_0)
     #define	MLCR_DEFAULT_5714		(MLCR_PCI_CTRL_SELECT     | \
     					 MLCR_LEGACY_PCI_MODE     | \
     					 MLCR_AUTO_SEEPROM_ACCESS | \
     					 MLCR_MISC_PINS_OUTPUT_2  | \
     					 MLCR_MISC_PINS_OUTPUT_1  | \
     					 MLCR_MISC_PINS_OUTPUT_0  | \
     					 MLCR_USE_SIG_DETECT)
     #define	MLCR_DEFAULT_5717		(MLCR_AUTO_SEEPROM_ACCESS)
     /*
      * Serial EEPROM Data/Address Registers (auto-access mode)
-...
     #define	NVM_CFG1_FLASH_MODE		0x00000001
     #define	NVM_SW_ARBITRATION_REG		0x7020
     #define	NVM_READ_REQ3			0X00008000
     #define	NVM_READ_REQ2			0X00004000
     #define	NVM_READ_REQ1			0X00002000
     #define	NVM_READ_REQ0			0X00001000
     #define	NVM_WON_REQ3			0X00000800
     #define	NVM_WON_REQ2			0X00000400
     #define	NVM_WON_REQ1			0X00000200
     #define	NVM_WON_REQ0			0X00000100
     #define	NVM_RESET_REQ3			0X00000080
     #define	NVM_RESET_REQ2			0X00000040
     #define	NVM_RESET_REQ1			0X00000020
     #define	NVM_RESET_REQ0			0X00000010
     #define	NVM_SET_REQ3			0X00000008
     #define	NVM_SET_REQ2			0X00000004
     #define	NVM_SET_REQ1			0X00000002
     #define	NVM_SET_REQ0			0X00000001
     #define	NVM_READ_REQ3			0x00008000
     #define	NVM_READ_REQ2			0x00004000
     #define	NVM_READ_REQ1			0x00002000
     #define	NVM_READ_REQ0			0x00001000
     #define	NVM_WON_REQ3			0x00000800
     #define	NVM_WON_REQ2			0x00000400
     #define	NVM_WON_REQ1			0x00000200
     #define	NVM_WON_REQ0			0x00000100
     #define	NVM_RESET_REQ3			0x00000080
     #define	NVM_RESET_REQ2			0x00000040
     #define	NVM_RESET_REQ1			0x00000020
     #define	NVM_RESET_REQ0			0x00000010
     #define	NVM_SET_REQ3			0x00000008
     #define	NVM_SET_REQ2			0x00000004
     #define	NVM_SET_REQ1			0x00000002
     #define	NVM_SET_REQ0			0x00000001
     #define	EEPROM_MAGIC			0x669955aa
     #define	EEPROM_MAGIC_FW			0xa5000000
     #define	EEPROM_MAGIC_FW_MSK		0xff000000
     #define	EEPROM_SB_FORMAT_MASK		0x00e00000
     #define	EEPROM_SB_FORMAT_1		0x00200000
     #define	EEPROM_SB_REVISION_MASK		0x001f0000
     #define	EEPROM_SB_REVISION_0		0x00000000
     #define	EEPROM_SB_REVISION_2		0x00020000
     #define	EEPROM_SB_REVISION_3		0x00030000
     #define	EEPROM_SB_REVISION_4		0x00040000
     #define	EEPROM_SB_REVISION_5		0x00050000
     #define	EEPROM_SB_REVISION_6		0x00060000
     #define	EEPROM_MAGIC_HW			0xabcd
     #define	EEPROM_MAGIC_HW_MSK		0xffff
     #define	NVM_DIR_START		0x18
     #define	NVM_DIR_END		0x78
     #define	NVM_DIRENT_SIZE		0xc
     #define	NVM_DIRTYPE_SHIFT	24
     #define	NVM_DIRTYPE_LENMSK	0x003fffff
     #define	NVM_DIRTYPE_ASFINI	1
     #define	NVM_DIRTYPE_EXTVPD	20
     #define	NVM_PTREV_BCVER		0x94
     #define	NVM_BCVER_MAJMSK	0x0000ff00
     #define	NVM_BCVER_MAJSFT	8
     #define	NVM_BCVER_MINMSK	0x000000ff
     /*
      * NVM access register
      * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
      * and BCM5715 only.
      */
     #define	NVM_ACCESS_REG			0X7024
     #define	NVM_WRITE_ENABLE		0X00000002
     #define	NVM_ACCESS_ENABLE		0X00000001
     #define	NVM_ACCESS_REG			0x7024
     #define	NVM_WRITE_ENABLE		0x00000002
     #define	NVM_ACCESS_ENABLE		0x00000001
     /*
      * TLP Control Register
-...
     /*
      * Vendor-specific MII registers
      */
     #define	MII_MMD_CTRL			0x0d /* MMD Access Control register */
     #define	MII_MMD_CTRL_DATA_NOINC		0x4000
     #define	MII_MMD_ADDRESS_DATA		0x0e /* MMD Address Data register */
     #define	MII_RXR_COUNTERS		0x14 /* Local/Remote Rx Counts */
     #define	MII_DSP_RW_PORT			0x15 /* DSP read/write port */
     #define	MII_DSP_CONTROL			0x16 /* DSP control register */
     #define	MII_DSP_ADDRESS			0x17 /* DSP address register */
     #define	MII_DSP_TAP26			0x001a
     #define	MII_DSP_TAP26_ALNOKO		0x0001
     #define	MII_DSP_TAP26_RMRXSTO		0x0002
     #define	MII_DSP_TAP26_OPCSINPT		0x0004
     #define	MII_DSP_CH34TP2			0x4022
     #define	MII_DSP_CH34TP2_HIBW01		0x017b
     #define	MII_EXT_CONTROL			MII_VENDOR(0)
     #define	MII_EXT_STATUS			MII_VENDOR(1)
     #define	MII_RCV_ERR_COUNT		MII_VENDOR(2)
-...
     #define	MII_AUX_CTRL_MISC_WRITE_ENABLE	0x8000
     #define	MII_AUX_CTRL_MISC_WIRE_SPEED	0x0010
     #define MII_AUX_CTRL_TX_6DB		0x0400
     #define MII_AUX_CTRL_SMDSP_ENA		0x0800
     /*
      * Write this value to the AUX control register
      * to select which shadow register will be read
-...
     #define	SBD_FLAG_IP_CKSUM		0x0002
     #define	SBD_FLAG_PACKET_END		0x0004
     #define	SBD_FLAG_IP_FRAG		0x0008
     #define	SBD_FLAG_JMB_PKT		0x0008
     #define	SBD_FLAG_IP_FRAG_END		0x0010
     #define	SBD_FLAG_VLAN_TAG		0x0040
-...
     #endif /* BGE_IPMI_ASF */
     /* APE registers.  Accessible through BAR1 */
     #define BGE_APE_GPIO_MSG		0x0008
     #define BGE_APE_GPIO_MSG_SHIFT		4
     #define BGE_APE_EVENT			0x000c
     #define  APE_EVENT_1			 0x00000001
     #define BGE_APE_LOCK_REQ		0x002c
     #define  APE_LOCK_REQ_DRIVER		 0x00001000
     #define BGE_APE_LOCK_GRANT		0x004c
     #define  APE_LOCK_GRANT_DRIVER		 0x00001000
     #define BGE_APE_STICKY_TMR		0x00b0
     /* APE shared memory.  Accessible through BAR1 */
     #define BGE_APE_SHMEM_BASE		0x4000
     #define BGE_APE_SEG_SIG			0x4000
     #define  APE_SEG_SIG_MAGIC		 0x41504521
     #define BGE_APE_FW_STATUS		0x400c
     #define  APE_FW_STATUS_READY		 0x00000100
     #define BGE_APE_FW_FEATURES		0x4010
     #define  BGE_APE_FW_FEATURE_NCSI	 0x00000002
     #define BGE_APE_FW_VERSION		0x4018
     #define  APE_FW_VERSION_MAJMSK		 0xff000000
     #define  APE_FW_VERSION_MAJSFT		 24
     #define  APE_FW_VERSION_MINMSK		 0x00ff0000
     #define  APE_FW_VERSION_MINSFT		 16
     #define  APE_FW_VERSION_REVMSK		 0x0000ff00
     #define  APE_FW_VERSION_REVSFT		 8
     #define  APE_FW_VERSION_BLDMSK		 0x000000ff
     #define BGE_APE_SEG_MSG_BUF_OFF		0x401c
     #define BGE_APE_SEG_MSG_BUF_LEN		0x4020
     #define BGE_APE_HOST_SEG_SIG		0x4200
     #define  APE_HOST_SEG_SIG_MAGIC		 0x484f5354
     #define BGE_APE_HOST_SEG_LEN		0x4204
     #define  APE_HOST_SEG_LEN_MAGIC		 0x00000020
     #define BGE_APE_HOST_INIT_COUNT		0x4208
     #define BGE_APE_HOST_DRIVER_ID		0x420c
     #define  APE_HOST_DRIVER_ID_SOLARIS	0xf4000000
     #define  APE_HOST_DRIVER_ID_MAGIC(maj, min) \
     	(APE_HOST_DRIVER_ID_SOLARIS | (maj & 0xff) << 16 | (min & 0xff) << 8)
     #define BGE_APE_HOST_BEHAVIOR		0x4210
     #define  APE_HOST_BEHAV_NO_PHYLOCK	 0x00000001
     #define BGE_APE_HOST_HEARTBEAT_INT_MS	0x4214
     #define  APE_HOST_HEARTBEAT_INT_DISABLE	 0
     #define  APE_HOST_HEARTBEAT_INT_5SEC	 5000
     #define BGE_APE_HOST_HEARTBEAT_COUNT	0x4218
     #define BGE_APE_HOST_DRVR_STATE		0x421c
     #define BGE_APE_HOST_DRVR_STATE_START	 0x00000001
     #define BGE_APE_HOST_DRVR_STATE_UNLOAD	 0x00000002
     #define BGE_APE_HOST_DRVR_STATE_WOL	 0x00000003
     #define BGE_APE_HOST_WOL_SPEED		0x4224
     #define BGE_APE_HOST_WOL_SPEED_AUTO	 0x00008000
     #define BGE_APE_EVENT_STATUS		0x4300
     #define  APE_EVENT_STATUS_DRIVER_EVNT	 0x00000010
     #define  APE_EVENT_STATUS_STATE_CHNGE	 0x00000500
     #define  APE_EVENT_STATUS_SCRTCHPD_READ	 0x00001600
     #define  APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
     #define  APE_EVENT_STATUS_STATE_START	 0x00010000
     #define  APE_EVENT_STATUS_STATE_UNLOAD	 0x00020000
     #define  APE_EVENT_STATUS_STATE_WOL	 0x00030000
     #define  APE_EVENT_STATUS_STATE_SUSPEND	 0x00040000
     #define  APE_EVENT_STATUS_EVENT_PENDING	 0x80000000
     #define BGE_APE_PER_LOCK_REQ		0x8400
     #define  APE_LOCK_PER_REQ_DRIVER	 0x00001000
     #define BGE_APE_PER_LOCK_GRANT		0x8420
     #define  APE_PER_LOCK_GRANT_DRIVER	 0x00001000
     /* APE convenience enumerations. */
     #define BGE_APE_LOCK_PHY0		0
     #define BGE_APE_LOCK_GRC		1
     #define BGE_APE_LOCK_PHY1		2
     #define BGE_APE_LOCK_PHY2		3
     #define BGE_APE_LOCK_MEM		4
     #define BGE_APE_LOCK_PHY3		5
     #define BGE_APE_LOCK_GPIO		7
     #ifdef __cplusplus
+    }
     #endif
     -- usr/src/uts/common/io/bge/bge_kstats.c	2014-02-12 08:11:52.976562500 -0500
     ++ usr/src/uts/common/io/bge/bge_kstats.c	2013-06-28 19:01:04.000000000 -0400
-...
      */
     /*
      * Copyright (c) 2010-2013, by Broadcom, Inc.
      * All Rights Reserved.
      */
     /*
      * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
      * Use is subject to license terms.
      */
-...
     	{ 18,				"&supported"		},
     	{ 19,				"&interface"		},
     	{ 20,				"nvtype"		},
     	{ 21,				"asic_rev_prod_id"	},
     	{ -1,				NULL 			}
     };
-...
     	bge_set_char_kstat(knp++,
     	    tmp & CHIP_FLAG_SERDES ? "serdes" : "copper");
     	(knp++)->value.ui64 =
     	    ((bgep->chipid.nvtype == BGE_NVTYPE_NONE) ||
     	     (bgep->chipid.nvtype == BGE_NVTYPE_UNKNOWN)) ?
 : bgep->chipid.nvtype;
     	(knp++)->value.ui64 = bgep->chipid.asic_rev_prod_id;
     	return (0);
+    }
-...
     	{ 25,				"buff_mgr_status"	},
     	{ 26,				"rcv_init_status"	},
     	{ 27,				"&version"		},
     	{ -1,				NULL 			}
     };
-...
+    	}
     	mutex_exit(bgep->genlock);
     	bge_set_char_kstat(knp++, bgep->version);
     	return (0);
+    }
-...
     	{ MII_INTR_STATUS,		"intr_status"		},
     	{ MII_INTR_MASK,		"intr_mask"		},
     	{ MII_HCD_STATUS,		"hcd_status"		},
     	{ EEE_MODE_REG,			"eee"			},
     	{ -1,				NULL }
     };
-...
     			knp->value.ui64 |= bge_mii_get16(bgep, MII_PHYIDL);
     			break;
     		case EEE_MODE_REG:
     			knp->value.ui64 = 0;
     			if (bgep->link_state == LINK_STATE_UP)
+    			{
     				knp->value.ui64 =
     				    (bge_reg_get32(bgep, EEE_MODE_REG) & 0x80) ?
 : 0;
+    			}
     			break;
     		default:
     			knp->value.ui64 = bge_mii_get16(bgep, ksip->index);
     			break;
-...
     	size /= sizeof (bge_ksindex_t);
     	ksp = kstat_create(BGE_DRIVER_NAME, instance, name, "net",
     	    KSTAT_TYPE_NAMED, size-1, KSTAT_FLAG_PERSISTENT);
     	    KSTAT_TYPE_NAMED, size-1, 0);
     	if (ksp == NULL)
     		return (NULL);
-...
     	bge_statistics_t *bstp;
     	bge_statistics_reg_t *pstats;
     	if (bgep->bge_chip_state == BGE_CHIP_FAULT) {
     	if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
     		return (EINVAL);
+    	}
-...
     	switch (stat) {
     	case MAC_STAT_IFSPEED:
     		*val = bgep->param_link_speed * 1000000ull;
     		*val = (bgep->link_state != LINK_STATE_UNKNOWN) ?
     		           (bgep->param_link_speed * 1000000ull) : 0;
     		break;
     	case MAC_STAT_MULTIRCV:
-...
     			*val = pstats->dot3StatsFrameTooLongs;
     		break;
     #if (MAC_VERSION > 1)
     	case ETHER_STAT_TOOSHORT_ERRORS:
     		if (bgep->chipid.statistic_type == BGE_STAT_BLK)
     			*val = bstp->s.etherStatsUndersizePkts;
     		else
     			*val = pstats->etherStatsUndersizePkts;
     		break;
     #endif
     	case ETHER_STAT_XCVR_ADDR:
     		*val = bgep->phy_mii_addr;
-...
     		*val = 1;
     		break;
     #if (MAC_VERSION > 1)
     	case ETHER_STAT_CAP_REMFAULT:
     		*val = 1;
     		break;
     #endif
     	case ETHER_STAT_ADV_CAP_1000FDX:
     		*val = bgep->param_adv_1000fdx;
-...
     		*val = bgep->param_adv_autoneg;
     		break;
     #if (MAC_VERSION > 1)
     	case ETHER_STAT_ADV_REMFAULT:
     		if (bgep->chipid.flags & CHIP_FLAG_SERDES)
     			*val = 0;
-...
     			mutex_exit(bgep->genlock);
+    		}
     		break;
     #endif
     	case ETHER_STAT_LP_CAP_1000FDX:
     		*val = bgep->param_lp_1000fdx;
-...
     		*val = bgep->param_lp_autoneg;
     		break;
     #if (MAC_VERSION > 1)
     	case ETHER_STAT_LP_REMFAULT:
     		if (bgep->chipid.flags & CHIP_FLAG_SERDES)
     			*val = 0;
-...
     			mutex_exit(bgep->genlock);
+    		}
     		break;
     #endif
     	case ETHER_STAT_LINK_ASMPAUSE:
     		*val = bgep->param_adv_asym_pause &&
-...
     		break;
     	case ETHER_STAT_LINK_DUPLEX:
     		*val = bgep->param_link_duplex;
     		*val = (bgep->link_state != LINK_STATE_UNKNOWN) ?
     		           bgep->param_link_duplex : LINK_DUPLEX_UNKNOWN;
     		break;
     	default:
     -- usr/src/uts/common/io/bge/bge_mii.c	2014-02-12 08:16:18.458007800 -0500
     ++ usr/src/uts/common/io/bge/bge_mii.c	2013-06-28 19:01:04.000000000 -0400
-...
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
      * Copyright (c) 2010-2013, by Broadcom, Inc.
      * All Rights Reserved.
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
      * All rights reserved.
      */
     #include "bge_impl.h"
-...
     #endif	/* BGE_DEBUGGING */
     static void
     bge_phy_toggle_auxctl_smdsp(bge_t *bgep,
                                 boolean_t enable)
+    {
     	uint16_t val;
     	val = bge_mii_get16(bgep, MII_AUX_CONTROL);
     	if (enable) {
     		val |= MII_AUX_CTRL_SMDSP_ENA;
     	} else {
     		val &= ~MII_AUX_CTRL_SMDSP_ENA;
+    	}
     	bge_mii_put16(bgep, MII_AUX_CONTROL, (val | MII_AUX_CTRL_TX_6DB));
+    }
     /*
      * Basic low-level function to probe for a PHY
+     *
-...
+    {
     	uint16_t miicfg;
     	uint32_t nicsig, niccfg;
     	int i;
     	BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep));
-...
     		 * order to clear any sticky bits (but they should
     		 * have been cleared by the RESET, I think).
     		 */
     		miicfg = bge_mii_get16(bgep, MII_STATUS);
     		miicfg = bge_mii_get16(bgep, MII_STATUS);
     		for (i = 0; i < 100; i++)
+    		{
     			drv_usecwait(40);
     			miicfg = bge_mii_get16(bgep, MII_STATUS);
+    		}
     		BGE_DEBUG(("bge_phy_probe: status 0x%x", miicfg));
     		/*
-...
+    }
     /*
      * End of Broadcom-derived workaround code				*
      * End of Broadcom-derived workaround code
      */
     static int
-...
     	uint16_t phy_status;
     	boolean_t reset_ok;
     	uint16_t extctrl, auxctrl;
     	int i;
     	BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown));
     	ASSERT(mutex_owned(bgep->genlock));
     	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
     	switch (MHCR_CHIP_ASIC_REV(bgep)) {
     	default:
     		/*
     		 * Shouldn't happen; it means we don't recognise this chip.
-...
     	case MHCR_CHIP_ASIC_REV_5906:
     	case MHCR_CHIP_ASIC_REV_5700:
     	case MHCR_CHIP_ASIC_REV_5701:
     	case MHCR_CHIP_ASIC_REV_5723:
     	case MHCR_CHIP_ASIC_REV_5723: /* 5717 and 5725 series as well */
     	case MHCR_CHIP_ASIC_REV_5721_5751:
     		/*
     		 * Just a plain reset; the "check" code breaks these chips
-...
     		break;
+    	}
     	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
     	switch (MHCR_CHIP_ASIC_REV(bgep)) {
     	case MHCR_CHIP_ASIC_REV_5705:
     	case MHCR_CHIP_ASIC_REV_5721_5751:
     		bge_phy_bit_err_fix(bgep);
-...
     	 * order to clear any sticky bits (but they should
     	 * have been cleared by the RESET, I think).
     	 */
     	phy_status = bge_mii_get16(bgep, MII_STATUS);
     	phy_status = bge_mii_get16(bgep, MII_STATUS);
     	for (i = 0; i < 100; i++)
+    	{
     		drv_usecwait(40);
     		phy_status = bge_mii_get16(bgep, MII_STATUS);
+    	}
     	BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status));
     	/*
-...
     	return (DDI_SUCCESS);
+    }
     boolean_t bge_eee_cap(bge_t * bgep)
+    {
         if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
               DEVICE_5725_SERIES_CHIPSETS(bgep)))
+        {
             /* EEE is not supported on this chip */
             BGE_DEBUG(("bge_eee: eee not supported (device 0x%x)",
                        bgep->chipid.device));
             return B_FALSE;
+        }
         switch (CHIP_ASIC_REV_PROD_ID(bgep))
+        {
         case CHIP_ASIC_REV_5717_B0: /* = CHIP_ASIC_REV_5718_B0 */
         case CHIP_ASIC_REV_5717_C0:
         /* case CHIP_ASIC_REV_5718_B0: */
         case CHIP_ASIC_REV_5719_A0:
         case CHIP_ASIC_REV_5719_A1:
         case CHIP_ASIC_REV_5720_A0:
         case CHIP_ASIC_REV_5725_A0:
         case CHIP_ASIC_REV_5727_B0:
             return B_TRUE;
         default:
             /* EEE is not supported on this asic rev */
             BGE_DEBUG(("bge_eee: eee not supported (asic rev 0x%08x)",
                        bgep->chipid.asic_rev));
             return B_FALSE;
+        }
+    }
     void bge_eee_init(bge_t * bgep)
+    {
         uint32_t val;
         BGE_TRACE(("bge_eee_init($%p)", (void *)bgep));
         ASSERT(mutex_owned(bgep->genlock));
         if (!bge_eee_cap(bgep))
+        {
             return;
+        }
         /* Enable MAC control of LPI */
         val = (EEE_LINK_IDLE_PCIE_NL0 | EEE_LINK_IDLE_UART_IDL);
         if (DEVICE_5725_SERIES_CHIPSETS(bgep))
             val |= EEE_LINK_IDLE_APE_TX_MT;
         bge_reg_put32(bgep, EEE_LINK_IDLE_CONTROL_REG, val);
         bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_20_1_US);
         val = (EEE_MODE_ERLY_L1_XIT_DET |
                EEE_MODE_LPI_IN_TX |
                EEE_MODE_LPI_IN_RX |
                EEE_MODE_EEE_ENABLE);
         if (bgep->chipid.device != DEVICE_ID_5717)
             val |= EEE_MODE_SND_IDX_DET_EN;
         //val |= EEE_MODE_APE_TX_DET_EN;
         if (!bgep->chipid.eee)
+        {
             val = 0;
+        }
         bge_reg_put32(bgep, EEE_MODE_REG, val);
         /* Set EEE timer debounce values */
         bge_reg_put32(bgep, EEE_DEBOUNCE_T1_CONTROL_REG,
                       (EEE_DEBOUNCE_T1_PCIEXIT_2047US |
                        EEE_DEBOUNCE_T1_LNKIDLE_2047US));
         bge_reg_put32(bgep, EEE_DEBOUNCE_T2_CONTROL_REG,
                       (EEE_DEBOUNCE_T2_APE_TX_2047US |
                        EEE_DEBOUNCE_T2_TXIDXEQ_2047US));
+    }
     void bge_eee_autoneg(bge_t * bgep, boolean_t adv_100fdx, boolean_t adv_1000fdx)
+    {
         uint32_t val;
         uint16_t mii_val;
         BGE_TRACE(("bge_eee_autoneg($%p)", (void *)bgep));
         ASSERT(mutex_owned(bgep->genlock));
         if (!bge_eee_cap(bgep))
+        {
             return;
+        }
         /* Disable LPI Requests */
         val = bge_reg_get32(bgep, EEE_MODE_REG);
         val &= ~EEE_MODE_LPI_ENABLE;
         bge_reg_put32(bgep, EEE_MODE_REG, val);
         bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
         mii_val = 0;
         if (bgep->chipid.eee)
+        {
             if (adv_100fdx)
+            {
                 mii_val |= EEE_CL45_D7_RESULT_STAT_LP_100TX;
+            }
             if (adv_1000fdx)
+            {
                 mii_val |= EEE_CL45_D7_RESULT_STAT_LP_1000T;
+            }
+        }
         /* Enable EEE advertisement for the specified mode(s)... */
         bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
         bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, MDIO_AN_EEE_ADV);
         bge_mii_put16(bgep, MII_MMD_CTRL, MII_MMD_CTRL_DATA_NOINC | MDIO_MMD_AN);
         bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, mii_val);
         /* Setup PHY DSP for EEE */
         switch (bgep->chipid.device)
+        {
         case DEVICE_ID_5717:
         case DEVICE_ID_5718:
         case DEVICE_ID_5719:
             /* If we advertised any EEE advertisements above... */
             if (mii_val)
+            {
                 mii_val = (MII_DSP_TAP26_ALNOKO |
                            MII_DSP_TAP26_RMRXSTO |
                            MII_DSP_TAP26_OPCSINPT);
+            }
             bge_phydsp_write(bgep, MII_DSP_TAP26, mii_val);
             /* fall through */
         case DEVICE_ID_5720:
         case DEVICE_ID_5725:
         case DEVICE_ID_5727:
             mii_val = bge_phydsp_read(bgep, MII_DSP_CH34TP2);
             bge_phydsp_write(bgep, MII_DSP_CH34TP2,
                              (mii_val | MII_DSP_CH34TP2_HIBW01));
+        }
         bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
+    }
     void bge_eee_adjust(bge_t * bgep)
+    {
         uint32_t val;
         uint16_t mii_val;
         BGE_TRACE(("bge_eee_adjust($%p, %d)", (void *)bgep));
         ASSERT(mutex_owned(bgep->genlock));
         if (!bge_eee_cap(bgep))
+        {
             return;
+        }
         bgep->eee_lpi_wait = 0;
         /* Check for PHY link status */
         if (bgep->param_link_up)
+        {
             BGE_DEBUG(("bge_eee_adjust: link status up"));
             /* XXX if duplex full and speed is 1000 or 100 then do following... */
             if (bgep->param_link_speed == 1000)
+            {
                 BGE_DEBUG(("bge_eee_adjust: eee timing for 1000Mb"));
                 bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_16_5_US);
+            }
             else if (bgep->param_link_speed == 100)
+            {
                 BGE_DEBUG(("bge_eee_adjust: eee timing for 100Mb"));
                 bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_36_US);
+            }
             /* Read PHY's EEE negotiation status */
             bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
             bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, EEE_CL45_D7_RESULT_STAT);
             bge_mii_put16(bgep, MII_MMD_CTRL, MII_MMD_CTRL_DATA_NOINC | MDIO_MMD_AN);
             mii_val = bge_mii_get16(bgep, MII_MMD_ADDRESS_DATA);
             /* Enable EEE LPI request if EEE negotiated */
             if ((mii_val == EEE_CL45_D7_RESULT_STAT_LP_1000T) ||
                 (mii_val == EEE_CL45_D7_RESULT_STAT_LP_100TX))
+            {
                 BGE_DEBUG(("bge_eee_adjust: eee negotiaton success, lpi scheduled"));
                 bgep->eee_lpi_wait = 2;
+            }
             else
+            {
                 BGE_DEBUG(("bge_eee_adjust: eee negotiation failed"));
+            }
+        }
         else
+        {
             BGE_DEBUG(("bge_eee_adjust: link status down"));
+        }
         if (!bgep->eee_lpi_wait)
+        {
             if (bgep->param_link_up)
+            {
                 bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
                 bge_phydsp_write(bgep, MII_DSP_TAP26, 0);
                 bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
+            }
             /* Disable LPI requests */
             val = bge_reg_get32(bgep, EEE_MODE_REG);
             val &= ~EEE_MODE_LPI_ENABLE;
             bge_reg_put32(bgep, EEE_MODE_REG, val);
+        }
+    }
     void bge_eee_enable(bge_t * bgep)
+    {
         uint32_t val;
         /* XXX check for EEE for 5717 family... */
         if (bgep->param_link_speed == 1000)
+        {
             bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
             bge_phydsp_write(bgep, MII_DSP_TAP26, (MII_DSP_TAP26_ALNOKO |
                                                    MII_DSP_TAP26_RMRXSTO));
             bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
+        }
         val = bge_reg_get32(bgep, EEE_MODE_REG);
         val |= EEE_MODE_LPI_ENABLE;
         bge_reg_put32(bgep, EEE_MODE_REG, val);
+    }
     /*
      * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities
      * and advertisements with the required settings as specified by the various
-...
     		break;
+    	}
     #endif	/* BGE_COPPER_WIRESPEED */
     	/* enable EEE on those chips that support it */
     	bge_eee_autoneg(bgep, adv_100fdx, adv_1000fdx);
     	return (DDI_SUCCESS);
+    }
-...
     	uint16_t aux;
     	uint_t mode;
     	boolean_t linkup;
     	int i;
     	/*
     	 * Step 10: read the status from the PHY (which is self-clearing
     	 * on read!); also read & clear the main (Ethernet) MAC status
     	 * (the relevant bits of this are write-one-to-clear).
     	 */
     	mii_status = bge_mii_get16(bgep, MII_STATUS);
     	for (i = 0; i < 100; i++)
+    	{
     		drv_usecwait(40);
     		mii_status = bge_mii_get16(bgep, MII_STATUS);
+    	}
     	emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
     	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status);
-...
     	 * known), there's nothing to do.
     	 */
     	if (mii_status == bgep->phy_gen_status && !recheck)
+    	{
     		BGE_DEBUG(("bge_check_copper: no link change"));
     		return (B_FALSE);
+    	}
     	do {
     		/*
     		 * Step 11: read AUX STATUS register to find speed/duplex
     		 */
     		aux = bge_mii_get16(bgep, MII_AUX_STATUS);
     		for (i = 0; i < 2000; i++)
+    		{
     			drv_usecwait(10);
     			aux = bge_mii_get16(bgep, MII_AUX_STATUS);
+    		}
     		BGE_CDB(bge_phydump, (bgep, mii_status, aux));
     		/*
-...
     		 */
     		bgep->phy_aux_status = aux;
     		bgep->phy_gen_status = mii_status;
     		mii_status = bge_mii_get16(bgep, MII_STATUS);
     		for (i = 0; i < 100; i++)
+    		{
     			drv_usecwait(40);
     			mii_status = bge_mii_get16(bgep, MII_STATUS);
+    		}
     	} while (mii_status != bgep->phy_gen_status);
     	/*
-...
     		bgep->param_link_duplex = bge_copper_link_duplex[mode];
+    	}
     	BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d",
     	    UPORDOWN(bgep->param_link_up),
     	    bgep->param_link_speed,
     	    bgep->param_link_duplex));
     	bge_eee_adjust(bgep);
     	bge_log(bgep, "bge_check_copper: link now %s speed %d duplex %d",
     	        UPORDOWN(bgep->param_link_up),
     	        bgep->param_link_speed,
     	        bgep->param_link_duplex);
     	return (B_TRUE);
+    }
-...
     	 * appropriately for the SerDes interface ...
     	 */
     	macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
     	if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
     		macmode |= ETHERNET_MODE_LINK_POLARITY;
     		macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
     	macmode &= ~ETHERNET_MODE_LINK_POLARITY;
     	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     	    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
     	    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
     		macmode |= ETHERNET_MODE_PORTMODE_GMII;
     	} else {
     		macmode &= ~ETHERNET_MODE_LINK_POLARITY;
     		macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
     		macmode |= ETHERNET_MODE_PORTMODE_TBI;
+    	}
     	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
-...
     		 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752,
     		 * BCM5714, and BCM5715 devices.
     		 */
     		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
     		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     		    DEVICE_5725_SERIES_CHIPSETS(bgep) ||
     		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
     			tx_status = bge_reg_get32(bgep,
     			    TRANSMIT_MAC_STATUS_REG);
     			linkup = BIS(tx_status, TRANSMIT_STATUS_LINK_UP);
     			emac_status = bge_reg_get32(bgep,
     			    ETHERNET_MAC_STATUS_REG);
     			bgep->serdes_status = emac_status;
     			/* clear write-one-to-clear bits in MAC status */
     			if ((emac_status & ETHERNET_STATUS_MI_COMPLETE) &&
     			    (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     			     DEVICE_5725_SERIES_CHIPSETS(bgep))) {
     			    emac_status |= (ETHERNET_STATUS_SYNC_CHANGED |
     			                    ETHERNET_STATUS_CFG_CHANGED);
+    			}
     			bge_reg_put32(bgep,
     			    ETHERNET_MAC_STATUS_REG, emac_status);
     			/*
     			 * If the link status has not changed then then
     			 * break. If it has loop around and recheck again.
     			 * Keep looping until the link status has not
     			 * changed.
     			 */
     			if ((linkup && linkup_old) ||
     			    (!linkup && !linkup_old)) {
     				emac_status &= ~ETHERNET_STATUS_LINK_CHANGED;
     				emac_status &= ~ETHERNET_STATUS_RECEIVING_CFG;
     				break;
+    			}
     			emac_status |= ETHERNET_STATUS_LINK_CHANGED;
     			emac_status |= ETHERNET_STATUS_RECEIVING_CFG;
     			if (linkup)
     				linkup_old = B_TRUE;
     			else
-...
+    	}
     	bgep->link_state = LINK_STATE_UNKNOWN;
     	BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d",
     	    UPORDOWN(bgep->param_link_up),
     	    bgep->param_link_speed,
     	    bgep->param_link_duplex));
     	bge_log(bgep, "bge_check_serdes: link now %s speed %d duplex %d",
     	        UPORDOWN(bgep->param_link_up),
     	        bgep->param_link_speed,
     	        bgep->param_link_duplex);
     	return (B_TRUE);
+    }
-...
     int
     bge_phys_init(bge_t *bgep)
+    {
     	uint32_t regval;
     	BGE_TRACE(("bge_phys_init($%p)", (void *)bgep));
     	mutex_enter(bgep->genlock);
-...
     	 * BCM800x PHY.
     	 */
     	bgep->phy_mii_addr = 1;
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
     		int regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
     		if (regval & CPMU_STATUS_FUN_NUM)
     			bgep->phy_mii_addr += 1;
     		bgep->phy_mii_addr = (bgep->pci_func + 1);
     		regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
     		if (regval & MEDIA_SELECTION_MODE)
     			bgep->phy_mii_addr += 7;
     			bgep->phy_mii_addr += 7; /* sgmii */
+    	}
     	if (bge_phy_probe(bgep)) {
-...
     boolean_t
     bge_phys_check(bge_t *bgep)
+    {
     	int32_t orig_state;
     	boolean_t recheck;
     	BGE_TRACE(("bge_phys_check($%p)", (void *)bgep));
     	ASSERT(mutex_owned(bgep->genlock));
     	orig_state = bgep->link_state;
     	recheck = orig_state == LINK_STATE_UNKNOWN;
     	recheck = (*bgep->physops->phys_check)(bgep, recheck);
     	if (!recheck)
     		return (B_FALSE);
     	return (B_TRUE);
     	/*
     	 * Force a link recheck if current state is unknown.
     	 * phys_check() returns TRUE if the link status changed, FALSE otherwise.
     	 */
     	return (*bgep->physops->phys_check)(bgep, (bgep->link_state ==
     	                                           LINK_STATE_UNKNOWN));
+    }
     -- usr/src/uts/common/io/bge/bge_send.c	2014-02-11 23:08:30.374023400 -0500
     ++ usr/src/uts/common/io/bge/bge_send.c	2013-06-28 19:01:04.000000000 -0400
-...
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
      * Copyright (c) 2010-2013, by Broadcom, Inc.
      * All Rights Reserved.
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
      * All rights reserved.
      */
     #include "bge_impl.h"
-...
     			hw_sbd_p->flags |= SBD_FLAG_IP_CKSUM;
     		if (pktp->pflags & HCK_FULLCKSUM)
     			hw_sbd_p->flags |= SBD_FLAG_TCP_UDP_CKSUM;
     		if (!(bgep->chipid.flags & CHIP_FLAG_NO_JUMBO) &&
     		    (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     		     DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
     		    (txbuf->copy_len > ETHERMAX))
     			hw_sbd_p->flags |= SBD_FLAG_JMB_PKT;
     		hw_sbd_p->flags |= SBD_FLAG_PACKET_END;
     		txfill_next = NEXT(txfill_next, BGE_SEND_BUF_MAX);
     -- usr/src/uts/common/io/bge/bge_chip2.c	2014-02-12 08:11:23.231445300 -0500
     ++ usr/src/uts/common/io/bge/bge_chip2.c	2014-02-13 18:48:57.482421800 -0500
-...
      */
     /*
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
      * Copyright (c) 2010-2013, by Broadcom, Inc.
      * All Rights Reserved.
      */
     /*
      * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
      * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
      * All rights reserved.
      */
     #include "bge_impl.h"
     #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
     #define	APE_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->ape_regs+(offset)))
     /*
      * Future features ... ?
-...
     boolean_t bge_relaxed_ordering = B_TRUE;
     /*
      * Property names
      */
     static char knownids_propname[] = "bge-known-subsystems";
     /*
      * Patchable globals:
+     *
      *	bge_autorecover
-...
     static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
     uint32_t bge_rx_ticks_norm = 128;
     uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
     uint32_t bge_tx_ticks_norm = 512;
     uint32_t bge_rx_count_norm = 8;
     uint32_t bge_tx_count_norm = 128;
-...
     	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
     #ifdef __sparc
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
     		regno = LE_32(regno);
+    	}
     #endif
     	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
     	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
-...
     	val = LE_32(val);
     #ifdef __sparc
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
     		regno = LE_32(regno);
+    	}
     #endif
     	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
     	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
-...
     	ddi_acc_handle_t handle;
     	uint16_t command;
     	uint32_t mhcr;
     	uint32_t prodid;
     	uint32_t pci_state;
     	uint16_t value16;
     	int i;
-...
     	 * byte-swapped value to it. So we just write zero first for simplicity.
     	 */
     	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     	    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
     		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
+    	}
     	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
     	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
     	cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK);
     	cidp->asic_rev_prod_id = 0;
     	if ((cidp->asic_rev & 0xf0000000) == CHIP_ASIC_REV_USE_PROD_ID_REG) {
     		prodid = CHIP_ASIC_REV_PROD_ID_REG;
     		if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     		    DEVICE_5725_SERIES_CHIPSETS(bgep)) {
     			prodid = CHIP_ASIC_REV_PROD_ID_GEN2_REG;
+    		}
     		cidp->asic_rev_prod_id = pci_config_get32(handle, prodid);
+    	}
     	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
     	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
-...
     	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
     	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
     	/* 5717 C0 is treated just like 5720 A0 */
     	if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
     	    DEVICE_ID_5717_C0) {
     		cidp->device = DEVICE_ID_5720;
+    	}
     	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
     	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
     	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
-...
     	 * see whether the host is truly up to date, and regenerate
     	 * its interrupt if not.
     	 */
     	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
     	    MHCR_ENABLE_TAGGED_STATUS_MODE |
     	    MHCR_MASK_INTERRUPT_MODE |
     	    MHCR_CLEAR_INTERRUPT_INTA;
     	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
     	       MHCR_ENABLE_PCI_STATE_RW |
     	       MHCR_ENABLE_TAGGED_STATUS_MODE |
     	       MHCR_MASK_INTERRUPT_MODE |
     	       MHCR_CLEAR_INTERRUPT_INTA;
     	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
     		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
     #ifdef	_BIG_ENDIAN
     	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
     #endif	/* _BIG_ENDIAN */
     	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
     		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
     	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
     #ifdef BGE_IPMI_ASF
     	bgep->asf_wordswapped = B_FALSE;
     #endif
     	pci_state = (PCISTATE_EXT_ROM_ENABLE | PCISTATE_EXT_ROM_RETRY);
     	/* allow reads and writes to the APE register and memory space */
     	if (bgep->ape_enabled) {
     		pci_state |= (PCISTATE_ALLOW_APE_CTLSPC_WR |
     		              PCISTATE_ALLOW_APE_SHMEM_WR |
     		              PCISTATE_ALLOW_APE_PSPACE_WR);
+    	}
     	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state);
     	/*
     	 * Step 1 (also step 7): Enable PCI Memory Space accesses
     	 *			 Disable Memory Write/Invalidate
-...
     		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
     			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
     			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
     		} else
     		} else if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
     		           DEVICE_5725_SERIES_CHIPSETS(bgep)) {
     			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
     			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
     		} else {
     			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
     			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
+    		}
+    	}
+    }
-...
     	uint64_t regval;
     #ifdef	__amd64
     	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
     	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
     	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||

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Feature #3446 » bge_illumos_kmays_021414-01.patch