Project

General

Profile

Bug #2732 ยป palign.patch

Richard PALO, 2014-09-20 04:24 PM

View differences:

usr/src/uts/i86pc/io/fipe/fipe_pm.c
99 99
#define	CPU_IDLE_CB_PRIO_FIPE		(CPU_IDLE_CB_PRIO_LOW_BASE + 0x4000000)
100 100

  
101 101
/* Structure to support power management profile. */
102
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_profiles)
102 103
static struct fipe_profile {
103 104
	uint32_t			idle_count;
104 105
	uint32_t			busy_threshold;
......
111 112
	{ 10,	40,	40,	75,	4 },
112 113
	{ 15,	50,	60,	100,	2 },
113 114
};
114
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_profiles)
115 115

  
116 116
/* Structure to store memory controller relative data. */
117
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_mc_ctrl)
117 118
static struct fipe_mc_ctrl {
118 119
	ddi_acc_handle_t		mc_pci_hdl;
119 120
	unsigned char			mc_thrtctrl;
......
122 123
	dev_info_t			*mc_dip;
123 124
	boolean_t			mc_initialized;
124 125
} fipe_mc_ctrl;
125
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_mc_ctrl)
126 126

  
127 127
/* Structure to store IOAT relative information. */
128
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_ioat_ctrl)
128 129
static struct fipe_ioat_control {
129 130
	kmutex_t			ioat_lock;
130 131
	boolean_t			ioat_ready;
......
147 148
	boolean_t			ioat_cancel;
148 149
	boolean_t			ioat_try_alloc;
149 150
} fipe_ioat_ctrl;
150
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_ioat_ctrl)
151 151

  
152
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_idle_ctrl)
152 153
static struct fipe_idle_ctrl {
153 154
	boolean_t			idle_ready;
154 155
	cpu_idle_callback_handle_t	cb_handle;
......
161 162
	/* Put here for cache efficiency, it should be in fipe_global_ctrl. */
162 163
	hrtime_t			tick_interval;
163 164
} fipe_idle_ctrl;
164
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_idle_ctrl)
165 165

  
166 166
/*
167 167
 * Global control structure.
168 168
 * Solaris idle thread has no reentrance issue, so it's enough to count CPUs
169 169
 * in idle state. Otherwise cpuset_t bitmap should be used to track idle CPUs.
170 170
 */
171
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_gbl_ctrl)
171 172
static struct fipe_global_ctrl {
172 173
	kmutex_t			lock;
173 174
	boolean_t			pm_enabled;
......
182 183
	kstat_t				*fipe_kstat;
183 184
#endif	/* FIPE_KSTAT_SUPPORT */
184 185
} fipe_gbl_ctrl;
185
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_gbl_ctrl)
186 186

  
187 187
#define	FIPE_CPU_STATE_PAD		(128 - \
188 188
	2 * sizeof (boolean_t) -  4 * sizeof (hrtime_t) - \
......
206 206
#pragma pack()
207 207

  
208 208
#ifdef	FIPE_KSTAT_SUPPORT
209
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_kstat)
209 210
static struct fipe_kstat_s {
210 211
	kstat_named_t		fipe_enabled;
211 212
	kstat_named_t		fipe_policy;
......
243 244
	{ "ioat_stop_fail_cnt",	KSTAT_DATA_UINT64 }
244 245
#endif	/* FIPE_KSTAT_DETAIL */
245 246
};
246
#pragma align CPU_CACHE_COHERENCE_SIZE(fipe_kstat)
247 247

  
248 248
#define	FIPE_KSTAT_INC(v)		\
249 249
	atomic_inc_64(&fipe_kstat.v.value.ui64)
    (1-1/1)