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Feature #3 » illumos-3-mpt.patch

Gordon Ross, 2017-04-04 12:34 AM

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/dev/null Thu Jan 01 00:00:00 1970 +0000 → usr/src/uts/common/io/scsi/adapters/mpi/mpi.c Sat Jul 31 18:01:44 2010 +1000
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/*
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 * Copyright (c) 2010 David Gwynne <dlg@animata.net>
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 *
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 * Permission to use, copy, modify, and distribute this software for any
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 * purpose with or without fee is hereby granted, provided that the above
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 * copyright notice and this permission notice appear in all copies.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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 */
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#include <sys/modctl.h>
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#include <sys/cmn_err.h>
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#include <sys/byteorder.h>
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#include <sys/pci.h>
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#include <sys/ddi.h>
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#include <sys/sunddi.h>
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#include <sys/debug.h>
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#include <sys/queue.h>
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#include <sys/scsi/scsi.h>
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#include <sys/note.h>
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#define MPI_DEBUG
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#ifdef MPI_DEBUG
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#define MPI_D_CCB		(1<<0)
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#define MPI_D_HBA		(1<<1)
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#define MPI_D_CAP		(1<<2)
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#define MPI_D_MISC		(1<<3)
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#define MPI_D_CMD		(1<<4)
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static int mpidebug = MPI_D_MISC | MPI_D_CMD;
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#define DPRINTF(mask, ...)				\
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do {							\
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	if ((mask) & mpidebug)				\
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		cmn_err(CE_NOTE, __VA_ARGS__);		\
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} while (0)
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#else
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#define DPRINTF(m, v...)
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#endif
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#pragma pack(1)
47

  
48
/*
49
 * System Interface Register Set
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 */
51

  
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#define MPI_DOORBELL		0x00
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/* doorbell read bits */
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#define  MPI_DOORBELL_STATE		(0xfUL<<28) /* ioc state */
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#define  MPI_DOORBELL_STATE_RESET	(0x0UL<<28)
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#define  MPI_DOORBELL_STATE_READY	(0x1UL<<28)
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#define  MPI_DOORBELL_STATE_OPER	(0x2UL<<28)
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#define  MPI_DOORBELL_STATE_FAULT	(0x4UL<<28)
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#define  MPI_DOORBELL_INUSE		(0x1UL<<27) /* doorbell used */
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#define  MPI_DOORBELL_WHOINIT		(0x7UL<<24) /* last to reset ioc */
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#define  MPI_DOORBELL_WHOINIT_NOONE	(0x0UL<<24) /* not initialized */
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#define  MPI_DOORBELL_WHOINIT_SYSBIOS	(0x1UL<<24) /* system bios */
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#define  MPI_DOORBELL_WHOINIT_ROMBIOS	(0x2UL<<24) /* rom bios */
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#define  MPI_DOORBELL_WHOINIT_PCIPEER	(0x3UL<<24) /* pci peer */
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#define  MPI_DOORBELL_WHOINIT_DRIVER	(0x4UL<<24) /* host driver */
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#define  MPI_DOORBELL_WHOINIT_MANUFACT	(0x5UL<<24) /* manufacturing */
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#define  MPI_DOORBELL_FAULT		(0xffff) /* fault code */
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#define  MPI_DOORBELL_FAULT_REQ_PCIPAR	0x8111 /* req msg pci parity err */
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#define  MPI_DOORBELL_FAULT_REQ_PCIBUS	0x8112 /* req msg pci bus err */
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#define  MPI_DOORBELL_FAULT_REP_PCIPAR	0x8113 /* reply msg pci parity err */
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#define  MPI_DOORBELL_FAULT_REP_PCIBUS	0x8114 /* reply msg pci bus err */
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#define  MPI_DOORBELL_FAULT_SND_PCIPAR	0x8115 /* data send pci parity err */
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#define  MPI_DOORBELL_FAULT_SND_PCIBUS	0x8116 /* data send pci bus err */
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#define  MPI_DOORBELL_FAULT_RCV_PCIPAR	0x8117 /* data recv pci parity err */
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#define  MPI_DOORBELL_FAULT_RCV_PCIBUS	0x8118 /* data recv pci bus err */
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/* doorbell write bits */
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#define  MPI_DOORBELL_FUNCTION_SHIFT	24
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#define  MPI_DOORBELL_FUNCTION_MASK	(0xffUL << MPI_DOORBELL_FUNCTION_SHIFT)
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#define  MPI_DOORBELL_FUNCTION(x)	\
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    (((x) << MPI_DOORBELL_FUNCTION_SHIFT) & MPI_DOORBELL_FUNCTION_MASK)
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#define  MPI_DOORBELL_DWORDS_SHIFT	16
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#define  MPI_DOORBELL_DWORDS_MASK	(0xffUL << MPI_DOORBELL_DWORDS_SHIFT)
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#define  MPI_DOORBELL_DWORDS(x)		\
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    (((x) << MPI_DOORBELL_DWORDS_SHIFT) & MPI_DOORBELL_DWORDS_MASK)
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#define  MPI_DOORBELL_DATA_MASK		0xffff
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87
#define MPI_WRITESEQ		0x04
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#define  MPI_WRITESEQ_VALUE		0x0000000f /* key value */
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#define  MPI_WRITESEQ_1			0x04
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#define  MPI_WRITESEQ_2			0x0b
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#define  MPI_WRITESEQ_3			0x02
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#define  MPI_WRITESEQ_4			0x07
93
#define  MPI_WRITESEQ_5			0x0d
94

  
95
#define MPI_HOSTDIAG		0x08
96
#define  MPI_HOSTDIAG_CLEARFBS		(1UL<<10) /* clear flash bad sig */
97
#define  MPI_HOSTDIAG_POICB		(1UL<<9) /* prevent ioc boot */
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#define  MPI_HOSTDIAG_DWRE		(1UL<<7) /* diag reg write enabled */
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#define  MPI_HOSTDIAG_FBS		(1UL<<6) /* flash bad sig */
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#define  MPI_HOSTDIAG_RESET_HIST	(1UL<<5) /* reset history */
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#define  MPI_HOSTDIAG_DIAGWR_EN		(1UL<<4) /* diagnostic write enabled */
102
#define  MPI_HOSTDIAG_RESET_ADAPTER	(1UL<<2) /* reset adapter */
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#define  MPI_HOSTDIAG_DISABLE_ARM	(1UL<<1) /* disable arm */
104
#define  MPI_HOSTDIAG_DIAGMEM_EN	(1UL<<0) /* diag mem enable */
105

  
106
#define MPI_TESTBASE		0x0c
107

  
108
#define MPI_DIAGRWDATA		0x10
109

  
110
#define MPI_DIAGRWADDR		0x18
111

  
112
#define MPI_INTR_STATUS		0x30
113
#define  MPI_INTR_STATUS_IOCDOORBELL	(1UL<<31) /* ioc doorbell status */
114
#define  MPI_INTR_STATUS_REPLY		(1UL<<3) /* reply message interrupt */
115
#define  MPI_INTR_STATUS_DOORBELL	(1UL<<0) /* doorbell interrupt */
116

  
117
#define MPI_INTR_MASK		0x34
118
#define  MPI_INTR_MASK_REPLY		(1UL<<3) /* reply message intr mask */
119
#define  MPI_INTR_MASK_DOORBELL		(1UL<<0) /* doorbell interrupt mask */
120

  
121
#define MPI_REQ_QUEUE		0x40
122

  
123
#define MPI_REPLY_QUEUE		0x44
124
#define  MPI_REPLY_QUEUE_ADDRESS	(1UL<<31) /* address reply */
125
#define  MPI_REPLY_QUEUE_ADDRESS_MASK	0x7fffffff
126
#define  MPI_REPLY_QUEUE_TYPE_MASK	(3UL<<29)
127
#define  MPI_REPLY_QUEUE_TYPE_INIT	(0UL<<29) /* scsi initiator reply */
128
#define  MPI_REPLY_QUEUE_TYPE_TARGET	(1UL<<29) /* scsi target reply */
129
#define  MPI_REPLY_QUEUE_TYPE_LAN	(2UL<<29) /* lan reply */
130
#define  MPI_REPLY_QUEUE_CONTEXT	0x1fffffff /* not address and type */
131

  
132
#define MPI_PRIREQ_QUEUE	0x48
133

  
134
/*
135
 * Scatter Gather Lists
136
 */
137

  
138
#define MPI_SGE_FL_LAST			(0x1UL<<31) /* last element in segment */
139
#define MPI_SGE_FL_EOB			(0x1UL<<30) /* last element of buffer */
140
#define MPI_SGE_FL_TYPE			(0x3UL<<28) /* element type */
141
#define  MPI_SGE_FL_TYPE_SIMPLE		(0x1UL<<28) /* simple element */
142
#define  MPI_SGE_FL_TYPE_CHAIN		(0x3UL<<28) /* chain element */
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#define  MPI_SGE_FL_TYPE_XACTCTX	(0x0UL<<28) /* transaction context */
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#define MPI_SGE_FL_LOCAL		(0x1UL<<27) /* local address */
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#define MPI_SGE_FL_DIR			(0x1UL<<26) /* direction */
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#define  MPI_SGE_FL_DIR_OUT		(0x1UL<<26)
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#define  MPI_SGE_FL_DIR_IN		(0x0UL<<26)
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#define MPI_SGE_FL_SIZE			(0x1UL<<25) /* address size */
149
#define  MPI_SGE_FL_SIZE_32		(0x0UL<<25)
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#define  MPI_SGE_FL_SIZE_64		(0x1UL<<25)
151
#define MPI_SGE_FL_EOL			(0x1UL<<24) /* end of list */
152
#define MPI_SGE_FLAGS_IOC_TO_HOST	(0x00)
153
#define MPI_SGE_FLAGS_HOST_TO_IOC	(0x04)
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155
struct mpi_sge {
156
	uint32_t		sg_hdr;
157
	uint32_t		sg_lo_addr;
158
	uint32_t		sg_hi_addr;
159
};
160

  
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struct mpi_fw_tce {
162
	uint8_t			reserved1;
163
	uint8_t			context_size;
164
	uint8_t			details_length;
165
	uint8_t			flags;
166

  
167
	uint32_t		reserved2;
168

  
169
	uint32_t		image_offset;
170

  
171
	uint32_t		image_size;
172
};
173

  
174
/*
175
 * Messages
176
 */
177

  
178
/* functions */
179
#define MPI_FUNCTION_SCSI_IO_REQUEST			(0x00)
180
#define MPI_FUNCTION_SCSI_TASK_MGMT			(0x01)
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#define MPI_FUNCTION_IOC_INIT				(0x02)
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#define MPI_FUNCTION_IOC_FACTS				(0x03)
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#define MPI_FUNCTION_CONFIG				(0x04)
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#define MPI_FUNCTION_PORT_FACTS				(0x05)
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#define MPI_FUNCTION_PORT_ENABLE			(0x06)
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#define MPI_FUNCTION_EVENT_NOTIFICATION			(0x07)
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#define MPI_FUNCTION_EVENT_ACK				(0x08)
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#define MPI_FUNCTION_FW_DOWNLOAD			(0x09)
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#define MPI_FUNCTION_TARGET_CMD_BUFFER_POST		(0x0A)
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#define MPI_FUNCTION_TARGET_ASSIST			(0x0B)
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#define MPI_FUNCTION_TARGET_STATUS_SEND			(0x0C)
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#define MPI_FUNCTION_TARGET_MODE_ABORT			(0x0D)
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#define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC	(0x0E) /* obsolete */
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#define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC		(0x0F) /* obsolete */
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#define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC	(0x10) /* obsolete */
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#define MPI_FUNCTION_TARGET_FC_ABORT			(0x11) /* obsolete */
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#define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST		(0x0E)
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#define MPI_FUNCTION_FC_LINK_SRVC_RSP			(0x0F)
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#define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND		(0x10)
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#define MPI_FUNCTION_FC_ABORT				(0x11)
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#define MPI_FUNCTION_FW_UPLOAD				(0x12)
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#define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND		(0x13)
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#define MPI_FUNCTION_FC_PRIMITIVE_SEND			(0x14)
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#define MPI_FUNCTION_RAID_ACTION			(0x15)
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#define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH		(0x16)
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#define MPI_FUNCTION_TOOLBOX				(0x17)
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210
#define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR		(0x18)
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212
#define MPI_FUNCTION_MAILBOX				(0x19)
213

  
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#define MPI_FUNCTION_LAN_SEND				(0x20)
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#define MPI_FUNCTION_LAN_RECEIVE			(0x21)
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#define MPI_FUNCTION_LAN_RESET				(0x22)
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#define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET		(0x40UL)
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#define MPI_FUNCTION_IO_UNIT_RESET			(0x41UL)
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#define MPI_FUNCTION_HANDSHAKE				(0x42UL)
221
#define MPI_FUNCTION_REPLY_FRAME_REMOVAL		(0x43UL)
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/* reply flags */
224
#define MPI_REP_FLAGS_CONT		(1UL<<7) /* continuation reply */
225

  
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#define MPI_REP_IOCSTATUS_AVAIL		(1UL<<15) /* logging info available */
227
#define MPI_REP_IOCSTATUS		(0x7fff) /* status */
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/* Common IOCStatus values for all replies */
230
#define  MPI_IOCSTATUS_SUCCESS				(0x0000)
231
#define  MPI_IOCSTATUS_INVALID_FUNCTION			(0x0001)
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#define  MPI_IOCSTATUS_BUSY				(0x0002)
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#define  MPI_IOCSTATUS_INVALID_SGL			(0x0003)
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#define  MPI_IOCSTATUS_INTERNAL_ERROR			(0x0004)
235
#define  MPI_IOCSTATUS_RESERVED				(0x0005)
236
#define  MPI_IOCSTATUS_INSUFFICIENT_RESOURCES		(0x0006)
237
#define  MPI_IOCSTATUS_INVALID_FIELD			(0x0007)
238
#define  MPI_IOCSTATUS_INVALID_STATE			(0x0008)
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#define  MPI_IOCSTATUS_OP_STATE_NOT_SUPPORTED		(0x0009)
240
/* Config IOCStatus values */
241
#define  MPI_IOCSTATUS_CONFIG_INVALID_ACTION		(0x0020)
242
#define  MPI_IOCSTATUS_CONFIG_INVALID_TYPE		(0x0021)
243
#define  MPI_IOCSTATUS_CONFIG_INVALID_PAGE		(0x0022)
244
#define  MPI_IOCSTATUS_CONFIG_INVALID_DATA		(0x0023)
245
#define  MPI_IOCSTATUS_CONFIG_NO_DEFAULTS		(0x0024)
246
#define  MPI_IOCSTATUS_CONFIG_CANT_COMMIT		(0x0025)
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/* SCSIIO Reply (SPI & FCP) initiator values */
248
#define  MPI_IOCSTATUS_SCSI_RECOVERED_ERROR		(0x0040)
249
#define  MPI_IOCSTATUS_SCSI_INVALID_BUS			(0x0041)
250
#define  MPI_IOCSTATUS_SCSI_INVALID_TARGETID		(0x0042)
251
#define  MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE		(0x0043)
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#define  MPI_IOCSTATUS_SCSI_DATA_OVERRUN		(0x0044)
253
#define  MPI_IOCSTATUS_SCSI_DATA_UNDERRUN		(0x0045)
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#define  MPI_IOCSTATUS_SCSI_IO_DATA_ERROR		(0x0046)
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#define  MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR		(0x0047)
256
#define  MPI_IOCSTATUS_SCSI_TASK_TERMINATED		(0x0048)
257
#define  MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH		(0x0049)
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#define  MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED		(0x004A)
259
#define  MPI_IOCSTATUS_SCSI_IOC_TERMINATED		(0x004B)
260
#define  MPI_IOCSTATUS_SCSI_EXT_TERMINATED		(0x004C)
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/* For use by SCSI Initiator and SCSI Target end-to-end data protection */
262
#define  MPI_IOCSTATUS_EEDP_GUARD_ERROR			(0x004D)
263
#define  MPI_IOCSTATUS_EEDP_REF_TAG_ERROR		(0x004E)
264
#define  MPI_IOCSTATUS_EEDP_APP_TAG_ERROR		(0x004F)
265
/* SCSI (SPI & FCP) target values */
266
#define  MPI_IOCSTATUS_TARGET_PRIORITY_IO		(0x0060)
267
#define  MPI_IOCSTATUS_TARGET_INVALID_PORT		(0x0061)
268
#define  MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX		(0x0062) /* obsolete */
269
#define  MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX		(0x0062)
270
#define  MPI_IOCSTATUS_TARGET_ABORTED			(0x0063)
271
#define  MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE		(0x0064)
272
#define  MPI_IOCSTATUS_TARGET_NO_CONNECTION		(0x0065)
273
#define  MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH	(0x006A)
274
#define  MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT		(0x006B)
275
#define  MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR		(0x006D)
276
#define  MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA	(0x006E)
277
#define  MPI_IOCSTATUS_TARGET_IU_TOO_SHORT		(0x006F)
278
/* Additional FCP target values */
279
#define  MPI_IOCSTATUS_TARGET_FC_ABORTED		(0x0066) /* obsolete */
280
#define  MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID		(0x0067) /* obsolete */
281
#define  MPI_IOCSTATUS_TARGET_FC_DID_INVALID		(0x0068) /* obsolete */
282
#define  MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT	(0x0069) /* obsolete */
283
/* Fibre Channel Direct Access values */
284
#define  MPI_IOCSTATUS_FC_ABORTED			(0x0066)
285
#define  MPI_IOCSTATUS_FC_RX_ID_INVALID			(0x0067)
286
#define  MPI_IOCSTATUS_FC_DID_INVALID			(0x0068)
287
#define  MPI_IOCSTATUS_FC_NODE_LOGGED_OUT		(0x0069)
288
#define  MPI_IOCSTATUS_FC_EXCHANGE_CANCELED		(0x006C)
289
/* LAN values */
290
#define  MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND		(0x0080)
291
#define  MPI_IOCSTATUS_LAN_DEVICE_FAILURE		(0x0081)
292
#define  MPI_IOCSTATUS_LAN_TRANSMIT_ERROR		(0x0082)
293
#define  MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED		(0x0083)
294
#define  MPI_IOCSTATUS_LAN_RECEIVE_ERROR		(0x0084)
295
#define  MPI_IOCSTATUS_LAN_RECEIVE_ABORTED		(0x0085)
296
#define  MPI_IOCSTATUS_LAN_PARTIAL_PACKET		(0x0086)
297
#define  MPI_IOCSTATUS_LAN_CANCELED			(0x0087)
298
/* Serial Attached SCSI values */
299
#define  MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED		(0x0090)
300
#define  MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN		(0x0091)
301
/* Inband values */
302
#define  MPI_IOCSTATUS_INBAND_ABORTED			(0x0098)
303
#define  MPI_IOCSTATUS_INBAND_NO_CONNECTION		(0x0099)
304
/* Diagnostic Tools values */
305
#define  MPI_IOCSTATUS_DIAGNOSTIC_RELEASED		(0x00A0)
306

  
307
#define MPI_REP_IOCLOGINFO_TYPE		(0xfUL<<28) /* logging info type */
308
#define MPI_REP_IOCLOGINFO_TYPE_NONE	(0x0UL<<28)
309
#define MPI_REP_IOCLOGINFO_TYPE_SCSI	(0x1UL<<28)
310
#define MPI_REP_IOCLOGINFO_TYPE_FC	(0x2UL<<28)
311
#define MPI_REP_IOCLOGINFO_TYPE_SAS	(0x3UL<<28)
312
#define MPI_REP_IOCLOGINFO_TYPE_ISCSI	(0x4UL<<28)
313
#define MPI_REP_IOCLOGINFO_DATA		(0x0fffffff) /* logging info data */
314

  
315
/* event notification types */
316
#define MPI_EVENT_NONE					0x00
317
#define MPI_EVENT_LOG_DATA				0x01
318
#define MPI_EVENT_STATE_CHANGE				0x02
319
#define MPI_EVENT_UNIT_ATTENTION			0x03
320
#define MPI_EVENT_IOC_BUS_RESET				0x04
321
#define MPI_EVENT_EXT_BUS_RESET				0x05
322
#define MPI_EVENT_RESCAN				0x06
323
#define MPI_EVENT_LINK_STATUS_CHANGE			0x07
324
#define MPI_EVENT_LOOP_STATE_CHANGE			0x08
325
#define MPI_EVENT_LOGOUT				0x09
326
#define MPI_EVENT_EVENT_CHANGE				0x0a
327
#define MPI_EVENT_INTEGRATED_RAID			0x0b
328
#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE		0x0c
329
#define MPI_EVENT_ON_BUS_TIMER_EXPIRED			0x0d
330
#define MPI_EVENT_QUEUE_FULL				0x0e
331
#define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE		0x0f
332
#define MPI_EVENT_SAS_SES				0x10
333
#define MPI_EVENT_PERSISTENT_TABLE_FULL			0x11
334
#define MPI_EVENT_SAS_PHY_LINK_STATUS			0x12
335
#define MPI_EVENT_SAS_DISCOVERY_ERROR			0x13
336
#define MPI_EVENT_IR_RESYNC_UPDATE			0x14
337
#define MPI_EVENT_IR2					0x15
338
#define MPI_EVENT_SAS_DISCOVERY				0x16
339
#define MPI_EVENT_LOG_ENTRY_ADDED			0x21
340

  
341
/* messages */
342

  
343
#define MPI_WHOINIT_NOONE		0x00
344
#define MPI_WHOINIT_SYSTEM_BIOS		0x01
345
#define MPI_WHOINIT_ROM_BIOS		0x02
346
#define MPI_WHOINIT_PCI_PEER		0x03
347
#define MPI_WHOINIT_HOST_DRIVER		0x04
348
#define MPI_WHOINIT_MANUFACTURER	0x05
349

  
350
/* page address fields */
351
#define MPI_PAGE_ADDRESS_FC_BTID	(1UL<<24)	/* Bus Target ID */
352

  
353
/* default messages */
354

  
355
struct mpi_msg_request {
356
	uint8_t			reserved1;
357
	uint8_t			reserved2;
358
	uint8_t			chain_offset;
359
	uint8_t			function;
360

  
361
	uint8_t			reserved3;
362
	uint8_t			reserved4;
363
	uint8_t			reserved5;
364
	uint8_t			msg_flags;
365

  
366
	uint32_t		msg_context;
367
};
368

  
369
struct mpi_msg_reply {
370
	uint8_t			reserved1;
371
	uint8_t			reserved2;
372
	uint8_t			msg_length;
373
	uint8_t			function;
374

  
375
	uint8_t			reserved3;
376
	uint8_t			reserved4;
377
	uint8_t			reserved5;
378
	uint8_t			msg_flags;
379

  
380
	uint32_t		msg_context;
381

  
382
	uint8_t			reserved6;
383
	uint8_t			reserved7;
384
	uint16_t		ioc_status;
385

  
386
	uint32_t		ioc_loginfo;
387
};
388

  
389
/* ioc init */
390

  
391
struct mpi_msg_iocinit_request {
392
	uint8_t			whoinit;
393
	uint8_t			reserved1;
394
	uint8_t			chain_offset;
395
	uint8_t			function;
396

  
397
	uint8_t			flags;
398
#define MPI_IOCINIT_F_DISCARD_FW			(1UL<<0)
399
#define MPI_IOCINIT_F_ENABLE_HOST_FIFO			(1UL<<1)
400
#define MPI_IOCINIT_F_HOST_PG_BUF_PERSIST		(1UL<<2)
401
	uint8_t			max_devices;
402
	uint8_t			max_buses;
403
	uint8_t			msg_flags;
404

  
405
	uint32_t		msg_context;
406

  
407
	uint16_t		reply_frame_size;
408
	uint16_t		reserved2;
409

  
410
	uint32_t		host_mfa_hi_addr;
411

  
412
	uint32_t		sense_buffer_hi_addr;
413

  
414
	uint32_t		reply_fifo_host_signalling_addr;
415

  
416
	struct mpi_sge		host_page_buffer_sge;
417

  
418
	uint8_t			msg_version_min;
419
	uint8_t			msg_version_maj;
420

  
421
	uint8_t			hdr_version_unit;
422
	uint8_t			hdr_version_dev;
423
};
424

  
425
struct mpi_msg_iocinit_reply {
426
	uint8_t			whoinit;
427
	uint8_t			reserved1;
428
	uint8_t			msg_length;
429
	uint8_t			function;
430

  
431
	uint8_t			flags;
432
	uint8_t			max_devices;
433
	uint8_t			max_buses;
434
	uint8_t			msg_flags;
435

  
436
	uint32_t		msg_context;
437

  
438
	uint16_t		reserved2;
439
	uint16_t		ioc_status;
440

  
441
	uint32_t		ioc_loginfo;
442
};
443

  
444

  
445
/* ioc facts */
446
struct mpi_msg_iocfacts_request {
447
	uint8_t			reserved1;
448
	uint8_t			reserved2;
449
	uint8_t			chain_offset;
450
	uint8_t			function;
451

  
452
	uint8_t			reserved3;
453
	uint8_t			reserved4;
454
	uint8_t			reserved5;
455
	uint8_t			msg_flags;
456

  
457
	uint32_t		msg_context;
458
};
459

  
460
struct mpi_msg_iocfacts_reply {
461
	uint8_t			msg_version_min;
462
	uint8_t			msg_version_maj;
463
	uint8_t			msg_length;
464
	uint8_t			function;
465

  
466
	uint8_t			header_version_min;
467
	uint8_t			header_version_maj;
468
	uint8_t			ioc_number;
469
	uint8_t			msg_flags;
470

  
471
	uint32_t		msg_context;
472

  
473
	uint16_t		ioc_exceptions;
474
#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL	(1UL<<0)
475
#define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID		(1UL<<1)
476
#define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL		(1UL<<2)
477
#define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL	(1UL<<3)
478
	uint16_t		ioc_status;
479

  
480
	uint32_t		ioc_loginfo;
481

  
482
	uint8_t			max_chain_depth;
483
	uint8_t			whoinit;
484
	uint8_t			block_size;
485
	uint8_t			flags;
486
#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT		(1UL<<0)
487
#define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL	(1UL<<1)
488
#define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT	(1UL<<2)
489

  
490
	uint16_t		reply_queue_depth;
491
	uint16_t		request_frame_size;
492

  
493
	uint16_t		reserved1;
494
	uint16_t		product_id;	/* product id */
495

  
496
	uint32_t		current_host_mfa_hi_addr;
497

  
498
	uint16_t		global_credits;
499
	uint8_t			number_of_ports;
500
	uint8_t			event_state;
501

  
502
	uint32_t		current_sense_buffer_hi_addr;
503

  
504
	uint16_t		current_reply_frame_size;
505
	uint8_t			max_devices;
506
	uint8_t			max_buses;
507

  
508
	uint32_t		fw_image_size;
509

  
510
	uint32_t		ioc_capabilities;
511
#define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q		(1UL<<0)
512
#define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL	(1UL<<1)
513
#define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING	(1UL<<2)
514
#define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER	(1UL<<3)
515
#define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER		(1UL<<4)
516
#define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER		(1UL<<5)
517
#define MPI_IOCFACTS_CAPABILITY_EEDP			(1UL<<6)
518
#define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL		(1UL<<7)
519
#define MPI_IOCFACTS_CAPABILITY_MULTICAST		(1UL<<8)
520
#define MPI_IOCFACTS_CAPABILITY_SCSIIO32		(1UL<<9)
521
#define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16		(1UL<<10)
522

  
523
	uint8_t			fw_version_dev;
524
	uint8_t			fw_version_unit;
525
	uint8_t			fw_version_min;
526
	uint8_t			fw_version_maj;
527

  
528
	uint16_t		hi_priority_queue_depth;
529
	uint16_t		reserved2;
530

  
531
	struct mpi_sge		host_page_buffer_sge;
532

  
533
	uint32_t		reply_fifo_host_signalling_addr;
534
};
535

  
536
struct mpi_msg_portfacts_request {
537
	uint8_t			reserved1;
538
	uint8_t			reserved2;
539
	uint8_t			chain_offset;
540
	uint8_t			function;
541

  
542
	uint8_t			reserved3;
543
	uint8_t			reserved4;
544
	uint8_t			port_number;
545
	uint8_t			msg_flags;
546

  
547
	uint32_t		msg_context;
548

  
549
};
550

  
551
struct mpi_msg_portfacts_reply {
552
	uint16_t		reserved1;
553
	uint8_t			msg_length;
554
	uint8_t			function;
555

  
556
	uint16_t		reserved2;
557
	uint8_t			port_number;
558
	uint8_t			msg_flags;
559

  
560
	uint32_t		msg_context;
561

  
562
	uint16_t		reserved3;
563
	uint16_t		ioc_status;
564

  
565
	uint32_t		ioc_loginfo;
566

  
567
	uint8_t			reserved4;
568
	uint8_t			port_type;
569
#define MPI_PORTFACTS_PORTTYPE_INACTIVE			0x00
570
#define MPI_PORTFACTS_PORTTYPE_SCSI			0x01
571
#define MPI_PORTFACTS_PORTTYPE_FC			0x10
572
#define MPI_PORTFACTS_PORTTYPE_ISCSI			0x20
573
#define MPI_PORTFACTS_PORTTYPE_SAS			0x30
574

  
575
	uint16_t		max_devices;
576

  
577
	uint16_t		port_scsi_id;
578
	uint16_t		protocol_flags;
579
#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR		(1UL<<0)
580
#define MPI_PORTFACTS_PROTOCOL_LAN			(1UL<<1)
581
#define MPI_PORTFACTS_PROTOCOL_TARGET			(1UL<<2)
582
#define MPI_PORTFACTS_PROTOCOL_INITIATOR		(1UL<<3)
583

  
584
	uint16_t		max_posted_cmd_buffers;
585
	uint16_t		max_persistent_ids;
586

  
587
	uint16_t		max_lan_buckets;
588
	uint16_t		reserved5;
589

  
590
	uint32_t		reserved6;
591
};
592

  
593
struct mpi_msg_portenable_request {
594
	uint16_t		reserved1;
595
	uint8_t			chain_offset;
596
	uint8_t			function;
597

  
598
	uint16_t		reserved2;
599
	uint8_t			port_number;
600
	uint8_t			msg_flags;
601

  
602
	uint32_t		msg_context;
603
};
604

  
605
struct mpi_msg_portenable_reply {
606
	uint16_t		reserved1;
607
	uint8_t			msg_length;
608
	uint8_t			function;
609

  
610
	uint16_t		reserved2;
611
	uint8_t			port_number;
612
	uint8_t			msg_flags;
613

  
614
	uint32_t		msg_context;
615

  
616
	uint16_t		reserved3;
617
	uint16_t		ioc_status;
618

  
619
	uint32_t		ioc_loginfo;
620
};
621

  
622
struct mpi_msg_event_request {
623
	uint8_t			event_switch;
624
#define MPI_EVENT_SWITCH_ON				(0x01)
625
#define MPI_EVENT_SWITCH_OFF				(0x00)
626
	uint8_t			reserved1;
627
	uint8_t			chain_offset;
628
	uint8_t			function;
629

  
630
	uint8_t			reserved2[3];
631
	uint8_t			msg_flags;
632

  
633
	uint32_t		msg_context;
634
};
635

  
636
struct mpi_msg_event_reply {
637
	uint16_t		data_length;
638
	uint8_t			msg_length;
639
	uint8_t			function;
640

  
641
	uint16_t		reserved1;
642
	uint8_t			ack_required;
643
#define MPI_EVENT_ACK_REQUIRED				(0x01)
644
	uint8_t			msg_flags;
645
#define MPI_EVENT_FLAGS_REPLY_KEPT			(1UL<<7)
646

  
647
	uint32_t		msg_context;
648

  
649
	uint16_t		reserved2;
650
	uint16_t		ioc_status;
651

  
652
	uint32_t		ioc_loginfo;
653

  
654
	uint32_t		event;
655

  
656
	uint32_t		event_context;
657

  
658
	/* event data follows */
659
};
660

  
661
struct mpi_evt_change {
662
	uint8_t			event_state;
663
	uint8_t			reserved[3];
664
};
665

  
666
struct mpi_evt_link_status_change {
667
	uint8_t			state;
668
#define MPI_EVT_LINK_STATUS_CHANGE_OFFLINE		0x00
669
#define MPI_EVT_LINK_STATUS_CHANGE_ACTIVE		0x01
670
	uint8_t			_reserved1[3];
671

  
672
	uint8_t			_reserved2[1];
673
	uint8_t			port;
674
	uint8_t			_reserved3[2];
675
};
676

  
677
struct mpi_evt_loop_status_change {
678
	uint8_t			character4;
679
	uint8_t			character3;
680
	uint8_t			type;
681
#define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LIP		0x01
682
#define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LPE		0x02
683
#define MPI_EVT_LOOP_STATUS_CHANGE_TYPE_LPB		0x03
684
	uint8_t			_reserved1[1];
685

  
686
	uint8_t			_reserved2[1];
687
	uint8_t			port;
688
	uint8_t			_reserved3[2];
689
};
690

  
691
struct mpi_evt_logout {
692
	uint32_t		n_portid;
693

  
694
	uint8_t			alias_index;
695
	uint8_t			port;
696
	uint8_t			_reserved[2];
697
};
698

  
699
struct mpi_evt_sas_phy {
700
	uint8_t			phy_num;
701
	uint8_t			link_rates;
702
#define MPI_EVT_SASPHY_LINK_CUR(x)			(((x) & 0xf0) >> 4)
703
#define MPI_EVT_SASPHY_LINK_PREV(x)			((x) & 0x0f)
704
#define MPI_EVT_SASPHY_LINK_ENABLED			0x0
705
#define MPI_EVT_SASPHY_LINK_DISABLED			0x1
706
#define MPI_EVT_SASPHY_LINK_NEGFAIL			0x2
707
#define MPI_EVT_SASPHY_LINK_SATAOOB			0x3
708
#define MPI_EVT_SASPHY_LINK_1_5GBPS			0x8
709
#define MPI_EVT_SASPHY_LINK_3_0GBPS			0x9
710
	uint16_t		dev_handle;
711

  
712
	uint64_t		sas_addr;
713
};
714

  
715
struct mpi_evt_sas_change {
716
	uint8_t			target;
717
	uint8_t			bus;
718
	uint8_t			reason;
719
#define MPI_EVT_SASCH_REASON_ADDED			0x03
720
#define MPI_EVT_SASCH_REASON_NOT_RESPONDING		0x04
721
#define MPI_EVT_SASCH_REASON_SMART_DATA			0x05
722
#define MPI_EVT_SASCH_REASON_NO_PERSIST_ADDED		0x06
723
#define MPI_EVT_SASCH_REASON_UNSUPPORTED		0x07
724
#define MPI_EVT_SASCH_REASON_INTERNAL_RESET		0x08
725
	uint8_t			reserved1;
726

  
727
	uint8_t			asc;
728
	uint8_t			ascq;
729
	uint16_t		dev_handle;
730

  
731
	uint32_t		device_info;
732
#define MPI_EVT_SASCH_INFO_ATAPI			(1UL<<13)
733
#define MPI_EVT_SASCH_INFO_LSI				(1UL<<12)
734
#define MPI_EVT_SASCH_INFO_DIRECT_ATTACHED		(1UL<<11)
735
#define MPI_EVT_SASCH_INFO_SSP				(1UL<<10)
736
#define MPI_EVT_SASCH_INFO_STP				(1UL<<9)
737
#define MPI_EVT_SASCH_INFO_SMP				(1UL<<8)
738
#define MPI_EVT_SASCH_INFO_SATA				(1UL<<7)
739
#define MPI_EVT_SASCH_INFO_SSP_INITIATOR		(1UL<<6)
740
#define MPI_EVT_SASCH_INFO_STP_INITIATOR		(1UL<<5)
741
#define MPI_EVT_SASCH_INFO_SMP_INITIATOR		(1UL<<4)
742
#define MPI_EVT_SASCH_INFO_SATA_HOST			(1UL<<3)
743
#define MPI_EVT_SASCH_INFO_TYPE_MASK			0x7
744
#define MPI_EVT_SASCH_INFO_TYPE_NONE			0x0
745
#define MPI_EVT_SASCH_INFO_TYPE_END			0x1
746
#define MPI_EVT_SASCH_INFO_TYPE_EDGE			0x2
747
#define MPI_EVT_SASCH_INFO_TYPE_FANOUT			0x3
748

  
749
	uint16_t		parent_dev_handle;
750
	uint8_t			phy_num;
751
	uint8_t			reserved2;
752

  
753
	uint64_t		sas_addr;
754
};
755

  
756
struct mpi_msg_eventack_request {
757
	uint16_t		reserved1;
758
	uint8_t			chain_offset;
759
	uint8_t			function;
760

  
761
	uint8_t			reserved2[3];
762
	uint8_t			msg_flags;
763

  
764
	uint32_t		msg_context;
765

  
766
	uint32_t		event;
767

  
768
	uint32_t		event_context;
769
};
770

  
771
struct mpi_msg_eventack_reply {
772
	uint16_t		reserved1;
773
	uint8_t			msg_length;
774
	uint8_t			function;
775

  
776
	uint8_t			reserved2[3];
777
	uint8_t			msg_flags;
778

  
779
	uint32_t		msg_context;
780

  
781
	uint16_t		reserved3;
782
	uint32_t		ioc_status;
783

  
784
	uint32_t		ioc_loginfo;
785
};
786

  
787
struct mpi_msg_fwupload_request {
788
	uint8_t			image_type;
789
#define MPI_FWUPLOAD_IMAGETYPE_IOC_FW			(0x00)
790
#define MPI_FWUPLOAD_IMAGETYPE_NV_FW			(0x01)
791
#define MPI_FWUPLOAD_IMAGETYPE_MPI_NV_FW		(0x02)
792
#define MPI_FWUPLOAD_IMAGETYPE_NV_DATA			(0x03)
793
#define MPI_FWUPLOAD_IMAGETYPE_BOOT			(0x04)
794
#define MPI_FWUPLOAD_IMAGETYPE_NV_BACKUP		(0x05)
795
	uint8_t			reserved1;
796
	uint8_t			chain_offset;
797
	uint8_t			function;
798

  
799
	uint8_t			reserved2[3];
800
	uint8_t			msg_flags;
801

  
802
	uint32_t		msg_context;
803

  
804
	struct mpi_fw_tce	tce;
805

  
806
	/* followed by an sgl */
807
};
808

  
809
struct mpi_msg_fwupload_reply {
810
	uint8_t			image_type;
811
	uint8_t			reserved1;
812
	uint8_t			msg_length;
813
	uint8_t			function;
814

  
815
	uint8_t			reserved2[3];
816
	uint8_t			msg_flags;
817

  
818
	uint32_t		msg_context;
819

  
820
	uint16_t		reserved3;
821
	uint16_t		ioc_status;
822

  
823
	uint32_t		ioc_loginfo;
824

  
825
	uint32_t		actual_image_size;
826
};
827

  
828
struct mpi_msg_scsi_io {
829
	uint8_t			target_id;
830
	uint8_t			bus;
831
	uint8_t			chain_offset;
832
	uint8_t			function;
833

  
834
	uint8_t			cdb_length;
835
	uint8_t			sense_buf_len;
836
	uint8_t			reserved1;
837
	uint8_t			msg_flags;
838
#define MPI_SCSIIO_EEDP					0xf0
839
#define MPI_SCSIIO_CMD_DATA_DIR				(1UL<<2)
840
#define MPI_SCSIIO_SENSE_BUF_LOC			(1UL<<1)
841
#define MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH			(1UL<<0)
842
#define  MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_32		(0UL<<0)
843
#define  MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_64		(1UL<<0)
844

  
845
	uint32_t		msg_context;
846

  
847
	uint8_t			lun[8];
848

  
849
	uint8_t			reserved2;
850
	uint8_t			tagging;
851
#define MPI_SCSIIO_ATTR_SIMPLE_Q			(0x0)
852
#define MPI_SCSIIO_ATTR_HEAD_OF_Q			(0x1)
853
#define MPI_SCSIIO_ATTR_ORDERED_Q			(0x2)
854
#define MPI_SCSIIO_ATTR_ACA_Q				(0x4)
855
#define MPI_SCSIIO_ATTR_UNTAGGED			(0x5)
856
#define MPI_SCSIIO_ATTR_NO_DISCONNECT			(0x7)
857
	uint8_t			reserved3;
858
	uint8_t			direction;
859
#define MPI_SCSIIO_DIR_NONE				(0x0)
860
#define MPI_SCSIIO_DIR_WRITE				(0x1)
861
#define MPI_SCSIIO_DIR_READ				(0x2)
862

  
863
#define MPI_CDB_LEN					16
864
	uint8_t			cdb[MPI_CDB_LEN];
865

  
866
	uint32_t		data_length;
867

  
868
	uint32_t		sense_buf_low_addr;
869

  
870
	/* followed by an sgl */
871
};
872

  
873
struct mpi_msg_scsi_io_error {
874
	uint8_t			target_id;
875
	uint8_t			bus;
876
	uint8_t			msg_length;
877
	uint8_t			function;
878

  
879
	uint8_t			cdb_length;
880
	uint8_t			sense_buf_len;
881
	uint8_t			reserved1;
882
	uint8_t			msg_flags;
883

  
884
	uint32_t		msg_context;
885

  
886
	uint8_t			scsi_status;
887
#define MPI_SCSIIO_ERR_STATUS_SUCCESS
888
#define MPI_SCSIIO_ERR_STATUS_CHECK_COND
889
#define MPI_SCSIIO_ERR_STATUS_BUSY
890
#define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE
891
#define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET
892
#define MPI_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT
893
#define MPI_SCSIIO_ERR_STATUS_CMD_TERM
894
#define MPI_SCSIIO_ERR_STATUS_TASK_SET_FULL
895
#define MPI_SCSIIO_ERR_STATUS_ACA_ACTIVE
896
	uint8_t			scsi_state;
897
#define MPI_SCSIIO_ERR_STATE_AUTOSENSE_VALID		(1UL<<0)
898
#define MPI_SCSIIO_ERR_STATE_AUTOSENSE_FAILED		(1UL<<2)
899
#define MPI_SCSIIO_ERR_STATE_NO_SCSI_STATUS		(1UL<<3)
900
#define MPI_SCSIIO_ERR_STATE_TERMINATED			(1UL<<4)
901
#define MPI_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID	(1UL<<5)
902
#define MPI_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED		(1UL<<6)
903
	uint16_t		ioc_status;
904

  
905
	uint32_t		ioc_loginfo;
906

  
907
	uint32_t		transfer_count;
908

  
909
	uint32_t		sense_count;
910

  
911
	uint32_t		response_info;
912

  
913
	uint16_t		tag;
914
	uint16_t		reserved2;
915
};
916

  
917
struct mpi_msg_scsi_task_request {
918
	uint8_t			target_id;
919
	uint8_t			bus;
920
	uint8_t			chain_offset;
921
	uint8_t			function;
922

  
923
	uint8_t			reserved1;
924
	uint8_t			task_type;
925
#define MPI_MSG_SCSI_TASK_TYPE_ABORT_TASK		(0x01)
926
#define MPI_MSG_SCSI_TASK_TYPE_ABRT_TASK_SET		(0x02)
927
#define MPI_MSG_SCSI_TASK_TYPE_TARGET_RESET		(0x03)
928
#define MPI_MSG_SCSI_TASK_TYPE_RESET_BUS		(0x04)
929
#define MPI_MSG_SCSI_TASK_TYPE_LOGICAL_UNIT_RESET	(0x05)
930
	uint8_t			reserved2;
931
	uint8_t			msg_flags;
932

  
933
	uint32_t		msg_context;
934

  
935
	uint8_t			lun[8];
936

  
937
	uint32_t		reserved3[7]; /* wtf? */
938

  
939
	uint32_t		target_msg_context;
940
};
941

  
942
struct mpi_msg_scsi_task_reply {
943
	uint8_t			target_id;
944
	uint8_t			bus;
945
	uint8_t			msg_length;
946
	uint8_t			function;
947

  
948
	uint8_t			response_code;
949
	uint8_t			task_type;
950
	uint8_t			reserved1;
951
	uint8_t			msg_flags;
952

  
953
	uint32_t		msg_context;
954

  
955
	uint16_t		reserved2;
956
	uint16_t		ioc_status;
957

  
958
	uint32_t		ioc_loginfo;
959

  
960
	uint32_t		termination_count;
961
};
962

  
963
struct mpi_msg_raid_action_request {
964
	uint8_t			action;
965
#define MPI_MSG_RAID_ACTION_STATUS			(0x00)
966
#define MPI_MSG_RAID_ACTION_INDICATOR_STRUCT		(0x01)
967
#define MPI_MSG_RAID_ACTION_CREATE_VOLUME		(0x02)
968
#define MPI_MSG_RAID_ACTION_DELETE_VOLUME		(0x03)
969
#define MPI_MSG_RAID_ACTION_DISABLE_VOLUME		(0x04)
970
#define MPI_MSG_RAID_ACTION_ENABLE_VOLUME		(0x05)
971
#define MPI_MSG_RAID_ACTION_QUIESCE_PHYSIO		(0x06)
972
#define MPI_MSG_RAID_ACTION_ENABLE_PHYSIO		(0x07)
973
#define MPI_MSG_RAID_ACTION_CH_VOL_SETTINGS		(0x08)
974
#define MPI_MSG_RAID_ACTION_PHYSDISK_OFFLINE		(0x0a)
975
#define MPI_MSG_RAID_ACTION_PHYSDISK_ONLINE		(0x0b)
976
#define MPI_MSG_RAID_ACTION_CH_PHYSDISK_SETTINGS	(0x0c)
977
#define MPI_MSG_RAID_ACTION_CREATE_PHYSDISK		(0x0d)
978
#define MPI_MSG_RAID_ACTION_DELETE_PHYSDISK		(0x0e)
979
#define MPI_MSG_RAID_ACTION_PHYSDISK_FAIL		(0x0f)
980
#define MPI_MSG_RAID_ACTION_ACTIVATE_VOLUME		(0x11)
981
#define MPI_MSG_RAID_ACTION_DEACTIVATE_VOLUME		(0x12)
982
#define MPI_MSG_RAID_ACTION_SET_RESYNC_RATE		(0x13)
983
#define MPI_MSG_RAID_ACTION_SET_SCRUB_RATE		(0x14)
984
#define MPI_MSG_RAID_ACTION_DEVICE_FW_UPDATE_MODE	(0x15)
985
#define MPI_MSG_RAID_ACTION_SET_VOL_NAME		(0x16)
986
	uint8_t			_reserved1;
987
	uint8_t			chain_offset;
988
	uint8_t			function;
989

  
990
	uint8_t			vol_id;
991
	uint8_t			vol_bus;
992
	uint8_t			phys_disk_num;
993
	uint8_t			message_flags;
994

  
995
	uint32_t		msg_context;
996

  
997
	uint32_t		_reserved2;
998

  
999
	uint32_t		data_word;
1000
	uint32_t		data_sge;
1001
};
1002

  
1003
struct mpi_msg_raid_action_reply {
1004
	uint8_t			action;
1005
	uint8_t			_reserved1;
1006
	uint8_t			message_length;
1007
	uint8_t			function;
1008

  
1009
	uint8_t			vol_id;
1010
	uint8_t			vol_bus;
1011
	uint8_t			phys_disk_num;
1012
	uint8_t			message_flags;
1013

  
1014
	uint32_t		message_context;
1015

  
1016
	uint16_t		action_status;
1017
#define MPI_RAID_ACTION_STATUS_OK			(0x0000)
1018
#define MPI_RAID_ACTION_STATUS_INVALID			(0x0001)
1019
#define MPI_RAID_ACTION_STATUS_FAILURE			(0x0002)
1020
#define MPI_RAID_ACTION_STATUS_IN_PROGRESS		(0x0004)
1021
	uint16_t		ioc_status;
1022

  
1023
	uint32_t		ioc_log_info;
1024

  
1025
	uint32_t		volume_status;
1026

  
1027
	uint32_t		action_data;
1028
};
1029

  
1030
struct mpi_cfg_hdr {
1031
	uint8_t			page_version;
1032
	uint8_t			page_length;
1033
	uint8_t			page_number;
1034
	uint8_t			page_type;
1035
#define MPI_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE		(0xf0)
1036
#define MPI_CONFIG_REQ_PAGE_TYPE_MASK			(0x0f)
1037
#define MPI_CONFIG_REQ_PAGE_TYPE_IO_UNIT		(0x00)
1038
#define MPI_CONFIG_REQ_PAGE_TYPE_IOC			(0x01)
1039
#define MPI_CONFIG_REQ_PAGE_TYPE_BIOS			(0x02)
1040
#define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_PORT		(0x03)
1041
#define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_DEV		(0x04)
1042
#define MPI_CONFIG_REQ_PAGE_TYPE_FC_PORT		(0x05)
1043
#define MPI_CONFIG_REQ_PAGE_TYPE_FC_DEV			(0x06)
1044
#define MPI_CONFIG_REQ_PAGE_TYPE_LAN			(0x07)
1045
#define MPI_CONFIG_REQ_PAGE_TYPE_RAID_VOL		(0x08)
1046
#define MPI_CONFIG_REQ_PAGE_TYPE_MANUFACTURING		(0x09)
1047
#define MPI_CONFIG_REQ_PAGE_TYPE_RAID_PD		(0x0A)
1048
#define MPI_CONFIG_REQ_PAGE_TYPE_INBAND			(0x0B)
1049
#define MPI_CONFIG_REQ_PAGE_TYPE_EXTENDED		(0x0F)
1050
};
1051

  
1052
struct mpi_ecfg_hdr {
1053
	uint8_t			page_version;
1054
	uint8_t			reserved1;
1055
	uint8_t			page_number;
1056
	uint8_t			page_type;
1057

  
1058
	uint16_t		ext_page_length;
1059
	uint8_t			ext_page_type;
1060
	uint8_t			reserved2;
1061
};
1062

  
1063
struct mpi_msg_config_request {
1064
	uint8_t			action;
1065
#define MPI_CONFIG_REQ_ACTION_PAGE_HEADER		(0x00)
1066
#define MPI_CONFIG_REQ_ACTION_PAGE_READ_CURRENT		(0x01)
1067
#define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT	(0x02)
1068
#define MPI_CONFIG_REQ_ACTION_PAGE_DEFAULT		(0x03)
1069
#define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM		(0x04)
1070
#define MPI_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT		(0x05)
1071
#define MPI_CONFIG_REQ_ACTION_PAGE_READ_NVRAM		(0x06)
1072
	uint8_t			reserved1;
1073
	uint8_t			chain_offset;
1074
	uint8_t			function;
1075

  
1076
	uint16_t		ext_page_len;
1077
	uint8_t			ext_page_type;
1078
#define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT		(0x10)
1079
#define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER	(0x11)
1080
#define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE		(0x12)
1081
#define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY		(0x13)
1082
#define MPI_CONFIG_REQ_EXTPAGE_TYPE_LOG			(0x14)
1083
	uint8_t			msg_flags;
1084

  
1085
	uint32_t		msg_context;
1086

  
1087
	uint32_t		reserved2[2];
1088

  
1089
	struct mpi_cfg_hdr	config_header;
1090

  
1091
	uint32_t		page_address;
1092
/* XXX lots of defns here */
1093

  
1094
	struct mpi_sge		page_buffer;
1095
};
1096

  
1097
struct mpi_msg_config_reply {
1098
	uint8_t			action;
1099
	uint8_t			reserved1;
1100
	uint8_t			msg_length;
1101
	uint8_t			function;
1102

  
1103
	uint16_t		ext_page_length;
1104
	uint8_t			ext_page_type;
1105
	uint8_t			msg_flags;
1106

  
1107
	uint32_t		msg_context;
1108

  
1109
	uint16_t		reserved2;
1110
	uint16_t		ioc_status;
1111

  
1112
	uint32_t		ioc_loginfo;
1113

  
1114
	struct mpi_cfg_hdr	config_header;
1115
};
1116

  
1117
struct mpi_cfg_spi_port_pg0 {
1118
	struct mpi_cfg_hdr	config_header;
1119

  
1120
	uint8_t			capabilities1;
1121
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_PACKETIZED	(1UL<<0)
1122
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_DT		(1UL<<1)
1123
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_QAS		(1UL<<2)
1124
	uint8_t			min_period;
1125
	uint8_t			max_offset;
1126
	uint8_t			capabilities2;
1127
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_IDP		(1UL<<3)
1128
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH		(1UL<<5)
1129
#define  MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_NARROW	(0UL<<5)
1130
#define  MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_WIDE	(1UL<<5)
1131
#define MPI_CFG_SPI_PORT_0_CAPABILITIES_AIP		(1UL<<7)
1132

  
1133
	uint8_t			signalling_type;
1134
#define MPI_CFG_SPI_PORT_0_SIGNAL_HVD			(0x1)
1135
#define MPI_CFG_SPI_PORT_0_SIGNAL_SE			(0x2)
1136
#define MPI_CFG_SPI_PORT_0_SIGNAL_LVD			(0x3)
1137
	uint16_t		reserved;
1138
	uint8_t			connected_id;
1139
#define  MPI_CFG_SPI_PORT_0_CONNECTEDID_BUSFREE		(0xfe)
1140
#define  MPI_CFG_SPI_PORT_0_CONNECTEDID_UNKNOWN		(0xff)
1141
};
1142

  
1143
struct mpi_cfg_spi_port_pg1 {
1144
	struct mpi_cfg_hdr	config_header;
1145

  
1146
	/* configuration */
1147
	uint8_t			port_scsi_id;
1148
	uint8_t			reserved1;
1149
	uint16_t		port_resp_ids;
1150

  
1151
	uint32_t		on_bus_timer_value;
1152

  
1153
	uint8_t			target_config;
1154
#define MPI_CFG_SPI_PORT_1_TARGCFG_TARGET_ONLY		(0x01)
1155
#define MPI_CFG_SPI_PORT_1_TARGCFG_INIT_TARGET		(0x02)
1156
	uint8_t			reserved2;
1157
	uint16_t		id_config;
1158
};
1159

  
1160
struct mpi_cfg_spi_port_pg2 {
1161
	struct mpi_cfg_hdr	config_header;
1162

  
1163
	uint32_t		port_flags;
1164
#define MPI_CFG_SPI_PORT_2_PORT_FLAGS_SCAN_HI2LOW	(1UL<<0)
1165
#define MPI_CFG_SPI_PORT_2_PORT_FLAGS_AVOID_RESET	(1UL<<2)
1166
#define MPI_CFG_SPI_PORT_2_PORT_FLAGS_ALT_CHS		(1UL<<3)
1167
#define MPI_CFG_SPI_PORT_2_PORT_FLAGS_TERM_DISABLED	(1UL<<4)
1168
#define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_CTL		(0x3UL<<5)
1169
#define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_BE	(0x0UL<<5)
1170
#define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_B	(0x1UL<<5)
1171
#define  MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_NONE	(0x3UL<<5)
1172

  
1173
	uint32_t		port_settings;
1174
#define MPI_CFG_SPI_PORT_2_PORT_SET_HOST_ID		(0x7UL<<0)
1175
#define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA		(0x3UL<<4)
1176
#define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_DISABLED	(0x0UL<<4)
1177
#define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS	(0x1UL<<4)
1178
#define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_OS	(0x2UL<<4)
1179
#define  MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS_OS	(0x3UL<<4)
1180
#define MPI_CFG_SPI_PORT_2_PORT_SET_REMOVABLE		(0x3UL<<6)
1181
#define MPI_CFG_SPI_PORT_2_PORT_SET_SPINUP_DELAY	(0xfUL<<8)
1182
#define MPI_CFG_SPI_PORT_2_PORT_SET_SYNC		(0x3UL<<12)
1183
#define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_SUPPORTED	(0x0UL<<12)
1184
#define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_NONE		(0x1UL<<12)
1185
#define  MPI_CFG_SPI_PORT_2_PORT_SET_NEG_ALL		(0x3UL<<12)
1186

  
1187
	struct {
1188
		uint8_t			timeout;
1189
		uint8_t			sync_factor;
1190
		uint16_t		device_flags;
1191
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_DISCONNECT_EN	(1UL<<0)
1192
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_ID_EN		(1UL<<1)
1193
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_LUN_EN		(1UL<<2)
1194
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_TAQ_Q_EN		(1UL<<3)
1195
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_WIDE_DIS		(1UL<<4)
1196
#define MPI_CFG_SPI_PORT_2_DEV_FLAG_BOOT_CHOICE		(1UL<<5)
1197
	}		device_settings[16];
1198
};
1199

  
1200
struct mpi_cfg_spi_dev_pg0 {
1201
	struct mpi_cfg_hdr	config_header;
1202

  
1203
	uint8_t			neg_params1;
1204
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_PACKETIZED		(1UL<<0)
1205
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_DUALXFERS		(1UL<<1)
1206
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_QAS			(1UL<<2)
1207
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_HOLD_MCS		(1UL<<3)
1208
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_WR_FLOW		(1UL<<4)
1209
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_RD_STRM		(1UL<<5)
1210
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_RTI			(1UL<<6)
1211
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_PCOMP_EN		(1UL<<7)
1212
	uint8_t			neg_period;
1213
	uint8_t			neg_offset;
1214
	uint8_t			neg_params2;
1215
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_IDP_EN		(1UL<<3)
1216
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH		(1UL<<5)
1217
#define  MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_NARROW	(0UL<<5)
1218
#define  MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_WIDE		(1UL<<5)
1219
#define MPI_CFG_SPI_DEV_0_NEGPARAMS_AIP			(1UL<<7)
1220

  
1221
	uint32_t		information;
1222
#define MPI_CFG_SPI_DEV_0_INFO_NEG_OCCURRED		(1UL<<0)
1223
#define MPI_CFG_SPI_DEV_0_INFO_SDTR_REJECTED		(1UL<<1)
1224
#define MPI_CFG_SPI_DEV_0_INFO_WDTR_REJECTED		(1UL<<2)
1225
#define MPI_CFG_SPI_DEV_0_INFO_PPR_REJECTED		(1UL<<3)
1226
};
1227

  
1228
struct mpi_cfg_spi_dev_pg1 {
1229
	struct mpi_cfg_hdr	config_header;
1230

  
1231
	uint8_t			req_params1;
1232
#define MPI_CFG_SPI_DEV_1_REQPARAMS_PACKETIZED		(1UL<<0)
1233
#define MPI_CFG_SPI_DEV_1_REQPARAMS_DUALXFERS		(1UL<<1)
1234
#define MPI_CFG_SPI_DEV_1_REQPARAMS_QAS			(1UL<<2)
1235
#define MPI_CFG_SPI_DEV_1_REQPARAMS_HOLD_MCS		(1UL<<3)
1236
#define MPI_CFG_SPI_DEV_1_REQPARAMS_WR_FLOW		(1UL<<4)
1237
#define MPI_CFG_SPI_DEV_1_REQPARAMS_RD_STRM		(1UL<<5)
1238
#define MPI_CFG_SPI_DEV_1_REQPARAMS_RTI			(1UL<<6)
1239
#define MPI_CFG_SPI_DEV_1_REQPARAMS_PCOMP_EN		(1UL<<7)
1240
	uint8_t			req_period;
1241
	uint8_t			req_offset;
1242
	uint8_t			req_params2;
1243
#define MPI_CFG_SPI_DEV_1_REQPARAMS_IDP_EN		(1UL<<3)
1244
#define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH		(1UL<<5)
1245
#define  MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_NARROW	(0UL<<5)
1246
#define  MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_WIDE		(1UL<<5)
1247
#define MPI_CFG_SPI_DEV_1_REQPARAMS_AIP			(1UL<<7)
1248

  
1249
	uint32_t		reserved;
1250

  
1251
	uint32_t		configuration;
1252
#define MPI_CFG_SPI_DEV_1_CONF_WDTR_DISALLOWED		(1UL<<1)
1253
#define MPI_CFG_SPI_DEV_1_CONF_SDTR_DISALLOWED		(1UL<<2)
1254
#define MPI_CFG_SPI_DEV_1_CONF_EXTPARAMS		(1UL<<3)
1255
#define MPI_CFG_SPI_DEV_1_CONF_FORCE_PPR		(1UL<<4)
1256
};
1257

  
1258
struct mpi_cfg_spi_dev_pg2 {
1259
	struct mpi_cfg_hdr	config_header;
1260

  
1261
	uint32_t		domain_validation;
1262
#define MPI_CFG_SPI_DEV_2_DV_ISI_ENABLED		(1UL<<4)
1263
#define MPI_CFG_SPI_DEV_2_DV_SECONDARY_DRV_EN		(1UL<<5)
1264
#define MPI_CFG_SPI_DEV_2_DV_SLEW_RATE_CTL		(0x7UL<<7)
1265
#define MPI_CFG_SPI_DEV_2_DV_PRIMARY_DRV_STRENGTH	(0x7UL<<10)
1266
#define MPI_CFG_SPI_DEV_2_DV_XCLKH_ST			(1UL<<28)
1267
#define MPI_CFG_SPI_DEV_2_DV_XCLKS_ST			(1UL<<29)
1268
#define MPI_CFG_SPI_DEV_2_DV_XCLKH_DT			(1UL<<30)
1269
#define MPI_CFG_SPI_DEV_2_DV_XCLKS_DT			(1UL<<31)
1270

  
1271
	uint32_t		parity_pipe_select;
1272
#define MPI_CFG_SPI_DEV_2_PARITY_PIPE_SELECT		(0x3)
1273

  
1274
	uint32_t		data_pipe_select;
1275
#define MPI_CFG_SPI_DEV_2_DATA_PIPE_SELECT(x)		(0x3UL<<((x)*2))
1276

  
1277
};
1278

  
1279
struct mpi_cfg_spi_dev_pg3 {
1280
	struct mpi_cfg_hdr	config_header;
1281

  
1282
	uint16_t		msg_reject_count;
1283
	uint16_t		phase_error_count;
1284

  
1285
	uint16_t		parity_error_count;
1286
	uint16_t		reserved;
1287
};
1288

  
1289
struct mpi_cfg_manufacturing_pg0 {
1290
	struct mpi_cfg_hdr	config_header;
1291

  
1292
	char			chip_name[16];
1293
	char			chip_revision[8];
1294
	char			board_name[16];
1295
	char			board_assembly[16];
1296
	char			board_tracer_number[16];
1297
};
1298

  
1299
struct mpi_cfg_ioc_pg1 {
1300
	struct mpi_cfg_hdr	config_header;
1301

  
1302
	uint32_t		flags;
1303
#define MPI_CFG_IOC_1_REPLY_COALESCING			(1UL<<0)
1304
#define MPI_CFG_IOC_1_CTX_REPLY_DISABLE			(1UL<<4)
1305

  
1306
	uint32_t		coalescing_timeout;
1307

  
1308
	uint8_t			coalescing_depth;
1309
	uint8_t			pci_slot_num;
1310
	uint8_t			_reserved[2];
1311
};
1312

  
1313
struct mpi_cfg_ioc_pg2 {
1314
	struct mpi_cfg_hdr	config_header;
1315

  
1316
	uint32_t		capabilities;
1317
#define MPI_CFG_IOC_2_CAPABILITIES_IS			(1UL<<0)
1318
#define MPI_CFG_IOC_2_CAPABILITIES_IME			(1UL<<1)
1319
#define MPI_CFG_IOC_2_CAPABILITIES_IM			(1UL<<2)
1320
#define  MPI_CFG_IOC_2_CAPABILITIES_RAID		( \
1321
    MPI_CFG_IOC_2_CAPABILITIES_IS | MPI_CFG_IOC_2_CAPABILITIES_IME | \
1322
    MPI_CFG_IOC_2_CAPABILITIES_IM)
1323
#define MPI_CFG_IOC_2_CAPABILITIES_SES			(1UL<<29)
1324
#define MPI_CFG_IOC_2_CAPABILITIES_SAFTE		(1UL<<30)
1325
#define MPI_CFG_IOC_2_CAPABILITIES_XCHANNEL		(1UL<<31)
1326

  
1327
	uint8_t			active_vols;
1328
	uint8_t			max_vols;
1329
	uint8_t			active_physdisks;
1330
	uint8_t			max_physdisks;
1331

  
1332
	/* followed by a list of mpi_cfg_raid_vol structs */
1333
};
1334

  
1335
struct mpi_cfg_raid_vol {
1336
	uint8_t			vol_id;
1337
	uint8_t			vol_bus;
1338
	uint8_t			vol_ioc;
1339
	uint8_t			vol_page;
1340

  
1341
	uint8_t			vol_type;
1342
#define MPI_CFG_RAID_TYPE_RAID_IS			(0x00)
1343
#define MPI_CFG_RAID_TYPE_RAID_IME			(0x01)
1344
#define MPI_CFG_RAID_TYPE_RAID_IM			(0x02)
1345
#define MPI_CFG_RAID_TYPE_RAID_5			(0x03)
1346
#define MPI_CFG_RAID_TYPE_RAID_6			(0x04)
1347
#define MPI_CFG_RAID_TYPE_RAID_10			(0x05)
1348
#define MPI_CFG_RAID_TYPE_RAID_50			(0x06)
1349
	uint8_t			flags;
1350
#define MPI_CFG_RAID_VOL_INACTIVE	(1UL<<3)
1351
	uint16_t		reserved;
1352
};
1353

  
1354
struct mpi_cfg_ioc_pg3 {
1355
	struct mpi_cfg_hdr	config_header;
1356

  
1357
	uint8_t			no_phys_disks;
1358
	uint8_t			reserved[3];
1359

  
1360
	/* followed by a list of mpi_cfg_raid_physdisk structs */
1361
};
1362

  
1363
struct mpi_cfg_raid_physdisk {
1364
	uint8_t			phys_disk_id;
1365
	uint8_t			phys_disk_bus;
1366
	uint8_t			phys_disk_ioc;
1367
	uint8_t			phys_disk_num;
1368
};
1369

  
1370
struct mpi_cfg_fc_port_pg0 {
1371
	struct mpi_cfg_hdr	config_header;
1372

  
1373
	uint32_t		flags;
1374

  
1375
	uint8_t			mpi_port_nr;
1376
	uint8_t			link_type;
1377
	uint8_t			port_state;
1378
	uint8_t			reserved1;
1379

  
1380
	uint32_t		port_id;
1381

  
1382
	uint64_t		wwnn;
1383

  
1384
	uint64_t		wwpn;
1385

  
1386
	uint32_t		supported_service_class;
1387

  
1388
	uint32_t		supported_speeds;
1389

  
1390
	uint32_t		current_speed;
1391

  
1392
	uint32_t		max_frame_size;
1393

  
1394
	uint64_t		fabric_wwnn;
1395

  
1396
	uint64_t		fabric_wwpn;
1397

  
1398
	uint32_t		discovered_port_count;
1399

  
1400
	uint32_t		max_initiators;
1401

  
1402
	uint8_t			max_aliases_supported;
1403
	uint8_t			max_hard_aliases_supported;
1404
	uint8_t			num_current_aliases;
1405
	uint8_t			reserved2;
1406
};
1407

  
1408
struct mpi_cfg_fc_port_pg1 {
1409
	struct mpi_cfg_hdr	config_header;
1410

  
1411
	uint32_t		flags;
1412

  
1413
	uint64_t		noseepromwwnn;
1414

  
1415
	uint64_t		noseepromwwpn;
1416

  
1417
	uint8_t			hard_alpa;
1418
	uint8_t			link_config;
1419
	uint8_t			topology_config;
1420
	uint8_t			alt_connector;
1421

  
1422
	uint8_t			num_req_aliases;
1423
	uint8_t			rr_tov;
1424
	uint8_t			initiator_dev_to;
1425
	uint8_t			initiator_lo_pend_to;
1426
};
1427

  
1428
struct mpi_cfg_fc_device_pg0 {
1429
	struct mpi_cfg_hdr	config_header;
1430

  
1431
	uint64_t		wwnn;
1432

  
1433
	uint64_t		wwpn;
1434

  
1435
	uint32_t		port_id;
1436

  
1437
	uint8_t			protocol;
1438
	uint8_t			flags;
1439
	uint16_t		bb_credit;
1440

  
1441
	uint16_t		max_rx_frame_size;
1442
	uint8_t			adisc_hard_alpa;
1443
	uint8_t			port_nr;
1444

  
1445
	uint8_t			fc_ph_low_version;
1446
	uint8_t			fc_ph_high_version;
1447
	uint8_t			current_target_id;
1448
	uint8_t			current_bus;
1449
};
1450

  
1451
struct mpi_raid_settings {
1452
	uint16_t		volume_settings;
1453
#define MPI_CFG_RAID_VOL_0_SETTINGS_WRITE_CACHE_EN	(1UL<<0)
1454
#define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART_ERR	(1UL<<1)
1455
#define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART	(1UL<<2)
1456
#define MPI_CFG_RAID_VOL_0_SETTINGS_AUTO_SWAP		(1UL<<3)
1457
#define MPI_CFG_RAID_VOL_0_SETTINGS_HI_PRI_RESYNC	(1UL<<4)
1458
#define MPI_CFG_RAID_VOL_0_SETTINGS_PROD_SUFFIX		(1UL<<5)
1459
#define MPI_CFG_RAID_VOL_0_SETTINGS_FAST_SCRUB		(1UL<<6) /* obsolete */
1460
#define MPI_CFG_RAID_VOL_0_SETTINGS_DEFAULTS		(1UL<<15)
1461
	uint8_t			hot_spare_pool;
1462
	uint8_t			reserved2;
1463
};
1464

  
1465
struct mpi_cfg_raid_vol_pg0 {
1466
	struct mpi_cfg_hdr	config_header;
1467

  
1468
	uint8_t			volume_id;
1469
	uint8_t			volume_bus;
1470
	uint8_t			volume_ioc;
1471
	uint8_t			volume_type;
1472

  
1473
	uint8_t			volume_status;
1474
#define MPI_CFG_RAID_VOL_0_STATUS_ENABLED		(1UL<<0)
1475
#define MPI_CFG_RAID_VOL_0_STATUS_QUIESCED		(1UL<<1)
1476
#define MPI_CFG_RAID_VOL_0_STATUS_RESYNCING		(1UL<<2)
1477
#define MPI_CFG_RAID_VOL_0_STATUS_ACTIVE		(1UL<<3)
1478
#define MPI_CFG_RAID_VOL_0_STATUS_BADBLOCK_FULL		(1UL<<4)
1479
	uint8_t			volume_state;
1480
#define MPI_CFG_RAID_VOL_0_STATE_OPTIMAL		(0x00)
1481
#define MPI_CFG_RAID_VOL_0_STATE_DEGRADED		(0x01)
1482
#define MPI_CFG_RAID_VOL_0_STATE_FAILED			(0x02)
1483
#define MPI_CFG_RAID_VOL_0_STATE_MISSING		(0x03)
1484
	uint16_t		_reserved1;
1485

  
1486
	struct mpi_raid_settings settings;
1487

  
1488
	uint32_t		max_lba;
1489

  
1490
	uint32_t		_reserved2;
1491

  
1492
	uint32_t		stripe_size;
1493

  
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