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Bug #1441 ยป webrev.3881.patch

Ken Mays, 2013-08-31 02:27 PM

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new/exception_lists/closed-bins Wed Aug 28 00:24:38 2013
13 13
./etc/snmp/conf
14 14
./etc/snmp/conf/mibiisa.reg
15 15
./etc/snmp/conf/snmp.conf
16
./kernel/drv/cpqary3
17
./kernel/drv/cpqary3.conf
18
./kernel/drv/amd64/cpqary3
16 19
./kernel/drv/iprb
17 20
./kernel/drv/amd64/iprb
18 21
./kernel/drv/pcn
19
-- old/usr/src/man/man7d/Makefile	Wed Aug 28 00:24:38 2013
22
++ new/usr/src/man/man7d/Makefile	Wed Aug 28 00:24:38 2013
......
29 29
	 	 	bscv.7d		\
30 30
	 	 	chxge.7d	\
31 31
	 	 	console.7d	\
32
			cpqary3.7d	\
32 33
	 	 	cpuid.7d	\
33 34
	 	 	dca.7d		\
34 35
	 	 	dcam1394.7d	\
35
-- /dev/null	Wed Aug 28 00:24:38 2013
36
++ new/usr/src/man/man7d/cpqary3.7d	Wed Aug 28 00:24:38 2013
......
1
.\"
2
.\" This file and its contents are supplied under the terms of the
3
.\" Common Development and Distribution License ("CDDL"), version 1.0.
4
.\" You may only use this file in accordance with the terms of version
5
.\" 1.0 of the CDDL.
6
.\"
7
.\" A full copy of the text of the CDDL should have accompanied this
8
.\" source.  A copy of the CDDL is also available via the Internet at
9
.\" http://www.illumos.org/license/CDDL.
10
.\"
11
.\"
12
.\" Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
13
.\"
14
.TH CPQARY3 7D "SunOS 5.11 Last Revised: Aug 26, 2013"
15
.SH NAME
16
.LP
17
cpqary3 - provides disk and SCSI tape support for HP Smart Array controllers
18
.LP
19
.SH DESCRIPTION
20
.LP
21
The cpqary3 module provides low-level interface routines between the common
22
disk I/O subsystem and the HP SMART Array controllers. The cpqary3 driver
23
provides disk and SCSI tape support for the HP Smart Array controllers.
24
.LP
25
Please refer to the cpqary3 release notes, for the supported HP Smart Array
26
Controllers and Storage boxes.
27
.LP
28
Each of the controller should be the sole initiator on a SCSI bus. Auto
29
configuration code determines if the adapter is present at the Configured
30
address and what types of devices are attached to it.
31
.SH CONFIGURATION
32
Use the Array Configuration Utility to configure the controllers. Each
33
controller can support up to 32 logical volumes. In addition, each controller
34
supports up to a maximum of 28 connected SCSI tape drives.
35
With 1.90 and later versions of cpqary3 driver, HP Smart Array SAS controllers,
36
having Firmware Revision 5.10 or later, will support 64 logical drives. This
37
firmware also supports Dual Domian Multipath configurations.
38
.LP
39
The driver attempts to initialize itself in accordance with the information
40
found in the configuration file, /kernel/drv/cpqary3.conf.
41
.LP
42
New component - hmaeventd which logs the storage events onto console and to the
43
Integrated Management Log is made a part of HPQhma 5.0.0 package, which is not
44
part of the operating system.  Therefore, by default, notify on event
45
functionality is disabled in the driver from 2.1.0 onwards.  Storage event
46
logging may be enabled in the driver by modifying cpqary3.conf to set the
47
cpqary3_noe property to "on".  Modification of driver properties requires
48
reloading the driver, which in most cases will occur only following a reboot of
49
the system.
50
.LP
51
The target driver's configuration file shall need entries if support is needed
52
for targets numbering greater than the default number of targets supported by
53
the corresponding target driver.
54
.LP
55
By default, entries for SCSI target numbers 0 to 15 are present in sd.conf.
56
Entries for target numbers 16 and above shall be added in SCSI class in the
57
sd.conf file for supporting corresponding logical volumes.
58
.LP
59
If SCSI tape drives are connected to the supported controllers, entries for
60
target IDs from 33 to 33+N must be added in the /kernel/drv/st.conf file under
61
\&'scsi' class, where N is the total number of SCSI tape drives connected to the
62
controller with largest number of tape drives connected to it, in the existing
63
configuration. For example, two supported controller, c1 and c2 are present in
64
the system. If controller c1 has two (2) tape drives and controller c2 has five
65
(5) tape drives connected, then entries for target IDs 33 thru 38 are required
66
under 'scsi' class in /kernel/drv/st.conf file. The maximum number of tape
67
drives that can be connected to a controller is 28. With 1.90 and later versions
68
of cpqary3 driver, if tape drives are connected to Smart Array SAS controllers,
69
then target ID entries for tape drives from 65 to 65+N must be added in
70
/kernel/drv/st.conf file under scsi class.
71
.SH FILES
72
.PD 0
73
.TP 25
74
.B /kernel/drv/cpqary3.conf
75
- configuration file for CPQary3
76
.PD
77
.SH "SEE ALSO"
78
.BR driver.conf (4),
79
.BR sd (7D),
80
.BR st (7D)
81
.LP
82
.SH NOTES
83
.LP
84
The Smart Array controllers supported by the current version of the
85
cpqary3 driver do not support 'format unit' SCSI command. Hence, selecting
86
\&'format' option under 'format' utility main menu is not supported. In addition,
87
the 'repair' option under 'format' utility main menu is not supported as this
88
operation is not applicable to Logical volumes connected to the supported Smart
89
Array controllers.
......
0
-- old/usr/src/pkg/manifests/driver-storage-cpqary3.mf	Wed Aug 28 00:24:38 2013
90
++ new/usr/src/pkg/manifests/driver-storage-cpqary3.mf	Wed Aug 28 00:24:38 2013
......
1 1
#
2
# CDDL HEADER START
2
# This file and its contents are supplied under the terms of the
3
# Common Development and Distribution License ("CDDL"), version 1.0.
4
# You may only use this file in accordance with the terms of version
5
# 1.0 of the CDDL.
3 6
#
4
# The contents of this file are subject to the terms of the
5
# Common Development and Distribution License (the "License").
6
# You may not use this file except in compliance with the License.
7
# A full copy of the text of the CDDL should have accompanied this
8
# source.  A copy of the CDDL is also available via the Internet at
9
# http://www.illumos.org/license/CDDL.
7 10
#
8
# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9
# or http://www.opensolaris.org/os/licensing.
10
# See the License for the specific language governing permissions
11
# and limitations under the License.
12
#
13
# When distributing Covered Code, include this CDDL HEADER in each
14
# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15
# If applicable, add the following below this CDDL HEADER, with the
16
# fields enclosed by brackets "[]" replaced with your own identifying
17
# information: Portions Copyright [yyyy] [name of copyright owner]
18
#
19
# CDDL HEADER END
20
#
21 11

  
22 12
#
23
# Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
13
# Copyright 2013 Joyent, Inc.  All rights reserved.
24 14
#
25 15

  
26
#
27
# The default for payload-bearing actions in this package is to appear in the
28
# global zone only.  See the include file for greater detail, as well as
29
# information about overriding the defaults.
30
#
31 16
<include global_zone_only_component>
32 17
set name=pkg.fmri value=pkg:/driver/storage/cpqary3@$(PKGVERS)
33
set name=pkg.description value="HP Smart Array HBA Driver 2.2.0.1"
34
set name=pkg.summary value="HP Smart Array HBA Driver 2.2.0.1"
18
set name=pkg.description value="HP SmartArray RAID Controller Driver"
19
set name=pkg.summary value="HP SmartArray RAID Controller Driver"
35 20
set name=info.classification \
36 21
    value=org.opensolaris.category.2008:Drivers/Storage
37 22
set name=variant.arch value=i386
38 23
dir path=kernel group=sys
39 24
dir path=kernel/drv group=sys
40 25
dir path=kernel/drv/$(ARCH64) group=sys
41
driver name=cpqary3 class=scsi \
42
    devlink=type=ddi_pseudo;minor1=cpqary3\tcpqary3\M2 \
26
dir path=usr/share/man
27
dir path=usr/share/man/man7d
28
driver name=cpqary3 class=scsi-self-identifying \
43 29
    alias=pci103c,3211 \
44 30
    alias=pci103c,3212 \
45 31
    alias=pci103c,3223 \
......
55 41
    alias=pci103c,3249 \
56 42
    alias=pci103c,324a \
57 43
    alias=pci103c,324b \
44
    alias=pci103c,3350 \
45
    alias=pci103c,3351 \
46
    alias=pci103c,3352 \
47
    alias=pci103c,3353 \
48
    alias=pci103c,3354 \
49
    alias=pci103c,3355 \
50
    alias=pci103c,3356 \
58 51
    alias=pcie11,4070 \
59 52
    alias=pcie11,4080 \
60 53
    alias=pcie11,4082 \
......
63 56
    alias=pcie11,409a \
64 57
    alias=pcie11,409b \
65 58
    alias=pcie11,409c \
66
    alias=pcie11,409d
59
    alias=pcie11,409d \
60
    alias=pcie11,409e
67 61
file path=kernel/drv/$(ARCH64)/cpqary3 group=sys
68 62
file path=kernel/drv/cpqary3 group=sys
69 63
file path=kernel/drv/cpqary3.conf group=sys
70
legacy pkg=CPQary3 desc="HP Smart Array HBA Driver 2.2.0.1" \
71
    name="HP Smart Array HBA Driver 2.2.0.1"
72
license cr_Sun license=cr_Sun
73
license lic_OSBL license=lic_OSBL
64
file path=usr/share/man/man7d/cpqary3.7d
65
license lic_CDDL license=lic_CDDL
74
-- old/usr/src/uts/common/Makefile.files	Wed Aug 28 00:24:38 2013
66
++ new/usr/src/uts/common/Makefile.files	Wed Aug 28 00:24:38 2013
......
2029 2029
MR_SAS_OBJS = ld_pd_map.o mr_sas.o mr_sas_tbolt.o mr_sas_list.o
2030 2030

  
2031 2031
#
2032
#	CPQARY3 module
2033
#
2034
CPQARY3_OBJS =	cpqary3.o cpqary3_noe.o cpqary3_talk2ctlr.o	\
2035
		cpqary3_isr.o cpqary3_transport.o cpqary3_mem.o	\
2036
		cpqary3_scsi.o cpqary3_util.o cpqary3_ioctl.o	\
2037
		cpqary3_bd.o
2038

  
2039
#
2032 2040
#	ISCSI_INITIATOR module
2033 2041
#
2034 2042
ISCSI_INITIATOR_OBJS =	chap.o iscsi_io.o iscsi_thread.o	\
2035
-- old/usr/src/uts/common/Makefile.rules	Wed Aug 28 00:24:38 2013
2043
++ new/usr/src/uts/common/Makefile.rules	Wed Aug 28 00:24:38 2013
......
701 701
	$(COMPILE.c) -o $@ $<
702 702
	$(CTFCONVERT_O)
703 703

  
704
$(OBJS_DIR)/%.o:		$(UTSBASE)/common/io/cpqary3/%.c
705
	$(COMPILE.c) -o $@ $<
706
	$(CTFCONVERT_O)
707

  
704 708
$(OBJS_DIR)/%.o:		$(UTSBASE)/common/io/dld/%.c
705 709
	$(COMPILE.c) -o $@ $<
706 710
	$(CTFCONVERT_O)
......
2074 2078
$(LINTS_DIR)/%.ln:		$(UTSBASE)/common/io/comstar/stmf/%.c
2075 2079
	@($(LHEAD) $(LINT.c) $< $(LTAIL))
2076 2080

  
2081
$(LINTS_DIR)/%.ln:		$(UTSBASE)/common/io/cpqary3/%.c
2082
	@($(LHEAD) $(LINT.c) $< $(LTAIL))
2083

  
2077 2084
$(LINTS_DIR)/%.ln:		$(UTSBASE)/common/io/dld/%.c
2078 2085
	@($(LHEAD) $(LINT.c) $< $(LTAIL))
2079 2086

  
2080
-- /dev/null	Wed Aug 28 00:24:39 2013
2087
++ new/usr/src/uts/common/io/cpqary3/cpqary3.c	Wed Aug 28 00:24:39 2013
......
1
/*
2
 * This file and its contents are supplied under the terms of the
3
 * Common Development and Distribution License ("CDDL"), version 1.0.
4
 * You may only use this file in accordance with the terms of version
5
 * 1.0 of the CDDL.
6
 *
7
 * A full copy of the text of the CDDL should have accompanied this
8
 * source.  A copy of the CDDL is also available via the Internet at
9
 * http://www.illumos.org/license/CDDL.
10
 */
11

  
12
/*
13
 * Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
14
 */
15

  
16
#include "cpqary3.h"
17

  
18
/*
19
 * Local Autoconfiguration Function Prototype Declations
20
 */
21

  
22
int cpqary3_attach(dev_info_t *, ddi_attach_cmd_t);
23
int cpqary3_detach(dev_info_t *, ddi_detach_cmd_t);
24
int cpqary3_open(dev_t *, int, int, cred_t *);
25
int cpqary3_close(dev_t, int, int, cred_t *);
26
int cpqary3_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
27

  
28
/*
29
 * Local Functions Definitions
30
 */
31

  
32
static void cpqary3_cleanup(cpqary3_t *, uint32_t);
33
static uint8_t cpqary3_update_ctlrdetails(cpqary3_t *, uint32_t *);
34
int8_t cpqary3_detect_target_geometry(cpqary3_t *);
35

  
36
/*
37
 * External Variable Definitions
38
 */
39

  
40
extern cpqary3_driver_info_t gdriver_info;
41

  
42
/*
43
 * Global Variables Definitions
44
 */
45

  
46
static char cpqary3_brief[]    =	"HP Smart Array Driver Ver 0.01J";
47
void *cpqary3_state;
48

  
49
/* HPQaculi Changes */
50

  
51
/*
52
 * HBA minor number schema
53
 *
54
 * The minor numbers for any minor device nodes that we create are
55
 * governed by the SCSA framework.  We use the macros below to
56
 * fabricate minor numbers for nodes that we own.
57
 *
58
 * See sys/impl/transport.h for more info.
59
 */
60

  
61
/* Macro to extract interface from minor number */
62
#define	CPQARY3_MINOR2INTERFACE(_x)  ((_x) & (TRAN_MINOR_MASK))
63

  
64
/* Base of range assigned to HBAs: */
65
#define	SCSA_MINOR_HBABASE  (32)
66

  
67
/* Our minor nodes: */
68
#define	CPQARY3_MINOR  (0 + SCSA_MINOR_HBABASE)
69

  
70
/* Convenience macros to convert device instances to minor numbers */
71
#define	CPQARY3_INST2x(_i, _x)    (((_i) << INST_MINOR_SHIFT) | (_x))
72
#define	CPQARY3_INST2CPQARY3(_i)  CPQARY3_INST2x(_i, CPQARY3_MINOR)
73

  
74
/* HPQacucli Changes */
75

  
76
/*
77
 * The Driver DMA Limit structure.
78
 * Data used for SMART Integrated Array Controller shall be used.
79
 */
80

  
81
ddi_dma_attr_t cpqary3_dma_attr = {
82
	DMA_ATTR_V0,		/* ddi_dma_attr version */
83
	0,			/* Low Address */
84
	0xFFFFFFFFFFFFFFFF,	/* High Address */
85
	0x00FFFFFF,		/* Max DMA Counter register */
86
	0x20,			/* Byte Alignment */
87
	0x20,			/* Burst Sizes : 32 Byte */
88
	DMA_UNIT_8,		/* Minimum DMA xfer Size */
89
	0xFFFFFFFF,		/* Maximum DMA xfer Size */
90
	/*
91
	 * Segment boundary restrictions
92
	 * The addr should not cross 4GB boundry.
93
	 * This is required to address an issue
94
	 * in the Surge ASIC, with earlier FW versions.
95
	 */
96
	0xFFFFFFFF,
97
	CPQARY3_SG_CNT,		/* Scatter/Gather List Length */
98
	512,			/* Device Granularity */
99
	0			/* DMA flags */
100
};
101

  
102
/*
103
 * The Device Access Attribute Structure.
104
 */
105

  
106
ddi_device_acc_attr_t cpqary3_dev_attributes = {
107
	DDI_DEVICE_ATTR_V0,
108
	DDI_STRUCTURE_LE_ACC,
109
	DDI_STRICTORDER_ACC
110
};
111

  
112
/*
113
 * Character-Block Operations Structure
114
 */
115

  
116
static struct cb_ops cpqary3_cb_ops = {
117
	/* HPQacucli Changes */
118
	scsi_hba_open,
119
	scsi_hba_close,
120
	/* HPQacucli Changes */
121
	nodev,			/* cb_strategy */
122
	nodev,			/* cb_print */
123
	nodev,			/* cb_dump */
124
	nodev,			/* cb_read */
125
	nodev,			/* cb_write */
126
	cpqary3_ioctl,		/* cb_ioctl */
127
	nodev,			/* cb_devmap */
128
	nodev,			/* cb_mmap */
129
	nodev,			/* cb_segmap */
130
	nochpoll,		/* cb_chpoll */
131
	ddi_prop_op,		/* cb_prop_op */
132
	NULL,			/* cb_stream */
133
	(int)(D_NEW|D_MP),	/* cb_flag */
134
	CB_REV,
135
	nodev,
136
	nodev
137
};
138

  
139
/*
140
 * Device Operations Structure
141
 */
142

  
143
static struct dev_ops cpqary3_dev_ops = {
144
	DEVO_REV,		/* Driver Build Version */
145
	0,			/* Driver reference count */
146
	nulldev,		/* Get Info */
147
	nulldev,		/* Identify not required */
148
	nulldev,		/* Probe, obselete for s2.6 and up */
149
	cpqary3_attach,		/* Attach routine */
150
	cpqary3_detach,		/* Detach routine */
151
	nodev,			/* Reset */
152
	&cpqary3_cb_ops,	/* Entry Points for C&B drivers */
153
	NULL,			/* Bus ops */
154
	nodev			/* cpqary3_power */
155
};
156

  
157
/*
158
 * Linkage structures
159
 */
160

  
161
static struct modldrv cpqary3_modldrv = {
162
	&mod_driverops,		/* Module Type - driver */
163
	cpqary3_brief,		/* Driver Desc */
164
	&cpqary3_dev_ops	/* Driver Ops */
165
};
166

  
167
static struct modlinkage cpqary3_modlinkage = {
168
	MODREV_1,		/* Loadable module rev. no. */
169
	&cpqary3_modldrv, 	/* Loadable module */
170
	NULL 			/* end */
171
};
172

  
173

  
174
/*
175
 * Function	:	_init
176
 * Description	:	This routine allocates soft state resources for the
177
 *			driver, registers the HBA with the system and
178
 *			adds the driver(loadable module).
179
 * Called By	:	Kernel
180
 * Parameters	:	None
181
 * Return Values:	0 / Non-Zero
182
 *			[as returned by the mod_install OS function]
183
 */
184
int
185
_init()
186
{
187
	int  retvalue;
188

  
189
	/*
190
	 * Allocate Soft State Resources; if failure, return.
191
	 */
192
	retvalue = ddi_soft_state_init(&cpqary3_state,
193
	    sizeof (cpqary3_t), MAX_CTLRS);
194
	VERIFY(retvalue == 0);
195

  
196
	/*
197
	 * Initialise the HBA Interface.
198
	 */
199
	if (!(retvalue = scsi_hba_init(&cpqary3_modlinkage))) {
200
		/* Load the driver */
201
		if ((retvalue = mod_install(&cpqary3_modlinkage))) {
202
			/*
203
			 * Failed to load the driver, undo HBA interface
204
			 * and soft state allocation.
205
			 */
206
			scsi_hba_fini(&cpqary3_modlinkage);
207
			ddi_soft_state_fini(&cpqary3_state);
208
		}
209
	} else {
210
		/*
211
		 * Failed to register HBA interface, undo all soft state
212
		 * allocation
213
		 */
214
		ddi_soft_state_fini(&cpqary3_state);
215
	}
216

  
217
	return (retvalue);
218
}
219

  
220
/*
221
 * Function	: 	_fini
222
 * Description	: 	This routine removes the loadable module, cancels the
223
 *			HBA registration and deallocates soft state resources.
224
 * Called By	: 	Kernel
225
 * Parameters	: 	None
226
 * Return Values: 	0 - Success / Non-Zero - Failure
227
 *			[as returned by the mod_remove(OS provided) function]
228
 */
229
int
230
_fini()
231
{
232
	int  retvalue;
233

  
234
	/* Unload the Driver(loadable module) */
235

  
236
	if ((retvalue = mod_remove(&cpqary3_modlinkage)) == 0) {
237

  
238
		/* Cancel the registeration for the HBA Interface */
239
		scsi_hba_fini(&cpqary3_modlinkage);
240

  
241
		/* dealloacte soft state resources of the driver */
242
		ddi_soft_state_fini(&cpqary3_state);
243
	}
244

  
245
	return (retvalue);
246
}
247

  
248
/*
249
 * Function	: 	_info
250
 * Description	: 	This routine returns information about the driver.
251
 * Called By	: 	Kernel
252
 * Parameters	: 	None
253
 * Return Values: 	0 / Non-Zero
254
 *			[as returned by mod_info(OS provided) function]
255
 */
256
int
257
_info(struct modinfo *modinfop)
258
{
259
	/*
260
	 * Get the module information.
261
	 */
262
	return (mod_info(&cpqary3_modlinkage, modinfop));
263
}
264

  
265

  
266
/*
267
 * Function	: 	cpqary3_attach
268
 * Description	: 	This routine initializes the driver specific soft state
269
 *			structure, initializes the HBA, interrupt handlers,
270
 *			memory pool, timeout handler, various mutex, creates the
271
 *			minor node.
272
 * Called By	: 	kernel
273
 * Parameters	: 	dip, command for attach
274
 * Return Values: 	DDI_SUCCESS / DDI_FAILURE
275
 *			[Success on overall initialization & configuration
276
 *			being successful. Failure if any of the initialization
277
 *			or any driver-specific mandatory configuration fails]
278
 */
279
int
280
cpqary3_attach(dev_info_t *dip, ddi_attach_cmd_t attach_cmd)
281
{
282
	int8_t		minor_node_name[14];
283
	uint32_t	instance;
284
	uint32_t	retvalue;
285
	uint32_t	cleanstatus = 0;
286
	cpqary3_t	*cpqary3p;		/* per-controller */
287
	ddi_dma_attr_t	tmp_dma_attr;
288

  
289
	DBG("CPQary3: _attach : Entering \n");
290

  
291
	/* Return Failure, If the Command is other than - DDI_ATTACH. */
292

  
293
	if (attach_cmd != DDI_ATTACH) {
294
		DBG1("CPQary3: Attach: Cmd 0x%x\n", attach_cmd);
295
		return (DDI_FAILURE);
296
	}
297

  
298
	/* Get the Instance of the Device */
299

  
300
	instance = ddi_get_instance(dip);
301

  
302
	/* Allocate the per-device-instance soft state structure */
303

  
304
	retvalue = ddi_soft_state_zalloc(cpqary3_state, instance);
305
	VERIFY(retvalue == 0);
306

  
307
	cleanstatus |= CPQARY3_SOFTSTATE_ALLOC_DONE;
308

  
309
	/* Per Controller Pointer */
310
	cpqary3p = ddi_get_soft_state(cpqary3_state, instance);
311
	if (!cpqary3p) {
312
		cmn_err(CE_WARN, "CPQary3: Soft State Retrieval Failed");
313
		cpqary3_cleanup(cpqary3p, cleanstatus);
314
		return (DDI_FAILURE);
315
	}
316

  
317
	/* Maintain a record in per-ctlr structure */
318
	cpqary3p->dip = dip;
319
	cpqary3p->instance = instance;
320

  
321
	DBG1("CPQary3: _attach : cpqary3p 0X%p\n", (void *)cpqary3p);
322
	DBG2("CPQary3: _attach : Instance <%d> Dip <0x%p>\n",
323
	    instance, (void *)dip);
324

  
325
	/* Get the User Configuration information from Driver's conf File */
326
	cpqary3_read_conf_file(dip, cpqary3p);
327

  
328
	/* Get and Map the HW Configuration */
329
	retvalue = cpqary3_update_ctlrdetails(cpqary3p, &cleanstatus);
330
	if (retvalue == CPQARY3_FAILURE) {
331
		cpqary3_cleanup(cpqary3p, cleanstatus);
332
		return (DDI_FAILURE);
333
	}
334

  
335
	/* Get the Cookie for hardware Interrupt Handler */
336
	if (ddi_get_iblock_cookie(dip, 0, &cpqary3p->hw_iblock_cookie) !=
337
	    DDI_SUCCESS) {
338
		cpqary3_cleanup(cpqary3p, cleanstatus);
339
		return (DDI_FAILURE);
340
	}
341

  
342
	/* Initialize Per Controller Mutex */
343
	mutex_init(&cpqary3p->hw_mutex, NULL, MUTEX_DRIVER,
344
	    (void *)cpqary3p->hw_iblock_cookie);
345

  
346
	cleanstatus |= CPQARY3_MUTEX_INIT_DONE;
347

  
348
	/* Get the Cookie for Soft(low level) Interrupt Handler */
349
	if (ddi_get_soft_iblock_cookie(dip, DDI_SOFTINT_HIGH,
350
	    &cpqary3p->sw_iblock_cookie) != DDI_SUCCESS) {
351
		cpqary3_cleanup(cpqary3p, cleanstatus);
352
		return (DDI_FAILURE);
353
	}
354

  
355
	/* Initialize the s/w Mutex */
356
	mutex_init(&cpqary3p->sw_mutex, NULL, MUTEX_DRIVER,
357
	    (void *)cpqary3p->sw_iblock_cookie);
358
	cleanstatus |= CPQARY3_SW_MUTEX_INIT_DONE;
359

  
360
	/* Initialize per Controller private details */
361
	retvalue = cpqary3_init_ctlr_resource(cpqary3p);
362
	if (retvalue != CPQARY3_SUCCESS) {
363
		cpqary3_cleanup(cpqary3p, cleanstatus);
364
		return (DDI_FAILURE);
365
	}
366
	cleanstatus |= CPQARY3_CTLR_CONFIG_DONE;
367

  
368
	/*
369
	 * Allocate HBA transport structure
370
	 */
371
	cpqary3p->hba_tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP);
372
	if (!cpqary3p->hba_tran) {
373
		cpqary3_cleanup(cpqary3p, cleanstatus);
374
		return (DDI_FAILURE);
375
	}
376
	cleanstatus |= CPQARY3_HBA_TRAN_ALLOC_DONE;
377

  
378
	/*
379
	 * Set private field for the HBA tran structure.
380
	 * Initialise the HBA tran entry points.
381
	 * Attach the controller to HBA.
382
	 */
383
	cpqary3_init_hbatran(cpqary3p);
384

  
385
	/* PERF */
386
	/* SG */
387
	tmp_dma_attr = cpqary3_dma_attr;
388
	tmp_dma_attr.dma_attr_sgllen = cpqary3p->sg_cnt;
389
	/* SG */
390
	/* PERF */
391
	/*
392
	 * Register the DMA attributes and the transport vectors
393
	 * of each instance of the  HBA device.
394
	 */
395
	if (scsi_hba_attach_setup(dip, &tmp_dma_attr, cpqary3p->hba_tran,
396
	    SCSI_HBA_TRAN_CLONE) == DDI_FAILURE) {
397
		cpqary3_cleanup(cpqary3p, cleanstatus);
398
		return (DDI_FAILURE);
399
	}
400
	cleanstatus |= CPQARY3_HBA_TRAN_ATTACH_DONE;
401

  
402
	/*
403
	 * Create a minor node for Ioctl interface.
404
	 * The nomenclature used will be "cpqary3" immediately followed by
405
	 * the current driver instance in the system.
406
	 * for e.g.: 	for 0th instance : cpqary30
407
	 * 				for 1th instance : cpqary31
408
	 */
409

  
410
	(void) sprintf(minor_node_name, "cpqary3,%d", instance);
411

  
412
	/* HPQacucli Changes */
413
	if (ddi_create_minor_node(dip, minor_node_name, S_IFCHR,
414
	    CPQARY3_INST2CPQARY3(instance), DDI_NT_SCSI_NEXUS, 0) ==
415
	    DDI_SUCCESS) {
416
		/* HPQacucli Changes */
417
		cleanstatus |= CPQARY3_CREATE_MINOR_NODE;
418
	} else {
419
		cmn_err(CE_NOTE, "CPQary3 : Failed to create minor node");
420
	}
421

  
422

  
423
	/* Register a timeout driver-routine to be called every 2 secs */
424
	cpqary3p->tick_tmout_id = timeout(cpqary3_tick_hdlr,
425
	    (caddr_t)cpqary3p, drv_usectohz(CPQARY3_TICKTMOUT_VALUE));
426
	cleanstatus |= CPQARY3_TICK_TMOUT_REGD;
427

  
428
	/* Register Software Interrupt Handler */
429
	if (ddi_add_softintr(dip,  DDI_SOFTINT_HIGH,
430
	    &cpqary3p->cpqary3_softintr_id, &cpqary3p->sw_iblock_cookie, NULL,
431
	    cpqary3_sw_isr, (caddr_t)cpqary3p) != DDI_SUCCESS) {
432
		cpqary3_cleanup(cpqary3p, cleanstatus);
433
		return (DDI_FAILURE);
434
	}
435
	cleanstatus |= CPQARY3_SW_INTR_HDLR_SET;
436

  
437
	/* Register Interrupt Handler */
438
	if (ddi_add_intr(dip, 0, &cpqary3p->hw_iblock_cookie, NULL,
439
	    cpqary3_hw_isr, (caddr_t)cpqary3p) != DDI_SUCCESS) {
440
		cpqary3_cleanup(cpqary3p, cleanstatus);
441
		return (DDI_FAILURE);
442
	}
443
	cleanstatus |= CPQARY3_INTR_HDLR_SET;
444

  
445
	/* Enable the Controller Interrupt */
446
	cpqary3_intr_onoff(cpqary3p, CPQARY3_INTR_ENABLE);
447
	if (cpqary3p->host_support & 0x4)
448
		cpqary3_lockup_intr_onoff(cpqary3p, CPQARY3_LOCKUP_INTR_ENABLE);
449

  
450
	/*
451
	 * We have come with hmaeventd - which logs the storage events on
452
	 * console as well as in IML. So we are commenting the NOE support in
453
	 * the driver
454
	 */
455

  
456
	/* NOE */
457
	if (cpqary3p->noe_support == 1) {
458
		/* Enable the Notification on Event in this controller */
459
		if (CPQARY3_SUCCESS ==
460
		    cpqary3_send_NOE_command(cpqary3p,
461
		    NULL, CPQARY3_NOE_INIT)) {
462
			cleanstatus |= CPQARY3_NOE_INIT_DONE;
463
		} else {
464
			cmn_err(CE_CONT, "CPQary3 : Failed to initialize "
465
			    "NOTIFICATION ON EVENT \n");
466
		}
467
	}
468
	/* NOE */
469

  
470
	/* Report that an Instance of the Driver is Attached Successfully */
471
	DBG2("CPQary3: Instance <%d> Attached to <%s>.\n",
472
	    cpqary3p->instance, cpqary3p->hba_name);
473

  
474
	ddi_report_dev(dip);
475

  
476
	/*
477
	 * Now update the num_ctlr
478
	 * This is required for the agents
479
	 */
480

  
481
	gdriver_info.num_ctlr++;
482

  
483

  
484
	DBG("CPQary3: _attach : Leaving \n");
485

  
486
	return (DDI_SUCCESS);
487

  
488
}
489

  
490
/*
491
 * Function	: 	cpqary3_detach
492
 * Description	: 	This routine removes the state associated with a
493
 * 			given instance of a device node prior to the
494
 * 			removal of that instance from the system
495
 * Called By	: 	kernel
496
 * Parameters	: 	dip, command for detach
497
 * Return Values: 	DDI_SUCCESS / DDI_FAILURE
498
 *			[failure ONLY if the command sent with this function
499
 *			as a paramter is not DETACH]
500
 */
501
int
502
cpqary3_detach(dev_info_t *dip, ddi_detach_cmd_t detach_cmd)
503
{
504
	cpqary3_t	*cpqary3p;
505
	scsi_hba_tran_t	*hba_tran;
506

  
507
	DBG("CPQary3 : _detach : Entering \n");
508

  
509
	/* Return failure, If Command is not DDI_DETACH */
510

  
511
	if (DDI_DETACH != detach_cmd) {
512
		DBG1("CPQary3: Detach Cmd %x\n", detach_cmd);
513
		return (DDI_FAILURE);
514
	}
515

  
516
	/*
517
	 *  Get scsi_hba_tran structure.
518
	 *  Get per controller structure.
519
	 */
520

  
521
	hba_tran = (scsi_hba_tran_t *)ddi_get_driver_private(dip);
522
	cpqary3p = (cpqary3_t *)hba_tran->tran_hba_private;
523

  
524
	/* Flush the cache */
525

  
526
	cpqary3_flush_cache(cpqary3p);
527

  
528
	/* Undo cpqary3_attach */
529

  
530
	cpqary3_cleanup(cpqary3p, CPQARY3_CLEAN_ALL);
531

  
532
	DBG("CPQary3 : _detach : Leaving \n");
533

  
534
	return (DDI_SUCCESS);
535

  
536
}
537

  
538
/*
539
 *	Function	: 	cpary3_open
540
 *	Description	: 	This routine does nothing.
541
 *				A pseudo fucntion for the entry point.
542
 *	Called By	: 	kernel
543
 *	Parameters	: 	irrelevant to the function here
544
 *	Return Values:  	0
545
 *				[A Dummy One]
546
 */
547
/* ARGSUSED */
548
int
549
cpqary3_open(dev_t *dev, int flag, int otype, cred_t *credp)
550
{
551
	DBG3("CPQary3: cpqary3_open (%p, %x, %p)\n",
552
	    (void *)dev, flag, (void *)credp);
553

  
554
	return (0);
555
}
556

  
557
/*
558
 *	Function	: 	cpary3_close
559
 *	Description	: 	This routine does nothing.
560
 *				A pseudo fucntion for the entry point.
561
 *	Called By	: 	kernel
562
 *	Parameters	: 	irrelevant to the function here
563
 *	Return Values:  	0
564
 *				[A Dummy One]
565
 */
566
/* ARGSUSED */
567
int
568
cpqary3_close(dev_t dev, int flag, int otype, cred_t *credp)
569
{
570
	DBG3("CPQary3: cpqary3_close (%p, %x, %p)\n",
571
	    (void *)dev, flag, (void *)credp);
572

  
573
	return (0);
574
}
575

  
576
/*
577
 *	Function	: 	cpary3_ioctl
578
 *	Description	: 	This routine services ioctl requests.
579
 *	Called By	: 	kernel
580
 *	Parameters	: 	Too many to list. Please look below !!!
581
 *	Return Values:  	0 / EINVAL / EFAULT /
582
 *				[0 on normal successful completion of the ioctl
583
 *				request]
584
 */
585
int
586
cpqary3_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
587
    int *retvaluep)
588
{
589
	minor_t		cpqary3_minor_num;
590
	cpqary3_t	*cpqary3p;
591
	int		instance;
592

  
593
	/*
594
	 * Get the soft state structure for this instance
595
	 * Return ENODEV if the structure does not exist.
596
	 */
597

  
598
	/*
599
	 * minor() call used in cpqary3_ioctl() returns minor number of the
600
	 * device which are in the
601
	 * range 0-255. if the minor number of the device is greater than 255,
602
	 * data will get truncated. so we are now using getminor(),
603
	 * instead of minor()
604
	 */
605

  
606
	if (EINVAL == (cpqary3_minor_num = getminor(dev))) {
607
		DBG("CPQary3: _ioctl: dev is NODEV\n");
608
		*retvaluep = ENODEV;
609
		return (*retvaluep);
610
	}
611

  
612
	/* HPQacucli Changes */
613

  
614
	/* get instance */
615
	instance = MINOR2INST(cpqary3_minor_num);
616

  
617
	cpqary3p = (cpqary3_t *)ddi_get_soft_state(cpqary3_state, instance);
618

  
619
	/* HPQacucli Changes */
620

  
621
	if (!cpqary3p) {
622
		DBG("CPQary3: _ioctl: Unable to get soft state");
623
		*retvaluep = ENODEV;
624
		return (*retvaluep);
625
	}
626

  
627
	/* HPQacucli Changes */
628

  
629
	/* check which interface is being requested */
630
	if (CPQARY3_MINOR2INTERFACE(cpqary3_minor_num) != CPQARY3_MINOR) {
631
		/* defer to SCSA */
632
		return (scsi_hba_ioctl(dev, cmd, arg, mode, credp, retvaluep));
633
	}
634

  
635
	/* HPQacucli Changes */
636

  
637
	switch (cmd) {
638
		case CPQARY3_IOCTL_DRIVER_INFO:
639
			*retvaluep =
640
			    cpqary3_ioctl_driver_info(arg, mode);
641
			break;
642

  
643
		case CPQARY3_IOCTL_CTLR_INFO:
644
			*retvaluep =
645
			    cpqary3_ioctl_ctlr_info(arg, cpqary3p, mode);
646
			break;
647

  
648
		case CPQARY3_IOCTL_BMIC_PASS:
649
			*retvaluep =
650
			    cpqary3_ioctl_bmic_pass(arg, cpqary3p, mode);
651
			break;
652

  
653
		case CPQARY3_IOCTL_SCSI_PASS:
654
			*retvaluep =
655
			    cpqary3_ioctl_scsi_pass(arg, cpqary3p, mode);
656
			break;
657

  
658
		default:
659
			*retvaluep = EINVAL;
660
			break;
661
	}
662
		return (*retvaluep);
663

  
664

  
665
}
666

  
667

  
668
/*
669
 * Function	: 	cqpary3_cleanup
670
 * Description	: 	This routine frees all allocated resources.
671
 * Called By	: 	kernel
672
 * Parameters	: 	per-controller, bit-map(stating what all to clean)
673
 * Return Values: 	None
674
 */
675
static void
676
cpqary3_cleanup(cpqary3_t *cpqary3p, uint32_t status)
677
{
678
	int8_t		node_name[10];
679
	clock_t		cpqary3_lbolt;
680
	uint32_t	targ;
681

  
682
	DBG1("CPQary3: _cleanup: Clean Code = %x \n", status);
683

  
684
	ASSERT(cpqary3p != NULL);
685

  
686
	/*
687
	 * Disable the NOE command
688
	 * Free the Command Memory Pool
689
	 * destroy all conditional variables
690
	 */
691

  
692
	/*
693
	 * We have removed NOE functionality from the
694
	 * driver. So commenting the below piece of code
695
	 */
696

  
697
	if (status & CPQARY3_NOE_INIT_DONE) {
698
		if (CPQARY3_SUCCESS == cpqary3_disable_NOE_command(cpqary3p)) {
699
			mutex_enter(&cpqary3p->hw_mutex);
700
			cpqary3_lbolt = ddi_get_lbolt();
701
			if (DDI_FAILURE ==
702
			    cv_timedwait_sig(&cpqary3p->cv_noe_wait,
703
			    &cpqary3p->hw_mutex,
704
			    cpqary3_lbolt + drv_usectohz(3000000))) {
705
				cmn_err(CE_NOTE,
706
				    "CPQary3: Resume signal for disable NOE "
707
				    "command not received \n");
708
			}
709
			mutex_exit(&cpqary3p->hw_mutex);
710
		}
711
	}
712

  
713
	/*
714
	 * Detach the device
715
	 * Free / Release / Destroy the following entities/resources:
716
	 * transport layer
717
	 * h/w & s/w interrupt handlers
718
	 * all mutex
719
	 * timeout handler
720
	 * target structure
721
	 * minor node
722
	 * soft state
723
	 * any register/memory mapping
724
	 */
725

  
726
	if (status & CPQARY3_INTR_HDLR_SET)
727
		ddi_remove_intr(cpqary3p->dip, 0, cpqary3p->hw_iblock_cookie);
728

  
729
	if (status & CPQARY3_SW_INTR_HDLR_SET)
730
		ddi_remove_softintr(cpqary3p->cpqary3_softintr_id);
731

  
732
	if ((status & CPQARY3_TICK_TMOUT_REGD) && cpqary3p->tick_tmout_id) {
733
		VERIFY(untimeout(cpqary3p->tick_tmout_id) >= 0);
734
		cpqary3p->tick_tmout_id = NULL;
735
	}
736

  
737
	if (status & CPQARY3_CREATE_MINOR_NODE) {
738
		(void) sprintf(node_name, "cpqary3%d", cpqary3p->instance);
739
		ddi_remove_minor_node(cpqary3p->dip, node_name);
740
	}
741

  
742
	if (status & CPQARY3_HBA_TRAN_ATTACH_DONE)
743
		(void) scsi_hba_detach(cpqary3p->dip);
744

  
745
	if (status & CPQARY3_HBA_TRAN_ALLOC_DONE)
746
		scsi_hba_tran_free(cpqary3p->hba_tran);
747

  
748
	if (status & CPQARY3_CTLR_CONFIG_DONE) {
749
		mutex_enter(&cpqary3p->hw_mutex);
750

  
751
		cv_destroy(&cpqary3p->cv_abort_wait);
752
		cv_destroy(&cpqary3p->cv_reset_wait);
753
		cv_destroy(&cpqary3p->cv_flushcache_wait);
754
		cv_destroy(&cpqary3p->cv_noe_wait);
755
		cv_destroy(&cpqary3p->cv_immediate_wait);
756
		cv_destroy(&cpqary3p->cv_ioctl_wait);
757

  
758
		for (targ = 0; targ < CPQARY3_MAX_TGT;  targ++) {
759
			if (cpqary3p->cpqary3_tgtp[targ] == NULL)
760
				continue;
761
			MEM_SFREE(cpqary3p->cpqary3_tgtp[targ],
762
			    sizeof (cpqary3_tgt_t));
763
		}
764

  
765
		mutex_exit(&cpqary3p->hw_mutex);
766

  
767
		cpqary3_memfini(cpqary3p, CPQARY3_MEMLIST_DONE |
768
		    CPQARY3_PHYCTGS_DONE | CPQARY3_CMDMEM_DONE);
769
	}
770

  
771
	if (status & CPQARY3_SW_MUTEX_INIT_DONE)
772
		mutex_destroy(&cpqary3p->sw_mutex);
773

  
774
	if (status & CPQARY3_MUTEX_INIT_DONE)
775
		mutex_destroy(&cpqary3p->hw_mutex);
776

  
777
	/*
778
	 * If this flag is set, free all mapped registers
779
	 */
780
	if (status & CPQARY3_MEM_MAPPED) {
781
		if (cpqary3p->idr_handle)
782
			ddi_regs_map_free(&cpqary3p->idr_handle);
783
		if (cpqary3p->isr_handle)
784
			ddi_regs_map_free(&cpqary3p->isr_handle);
785
		if (cpqary3p->imr_handle)
786
			ddi_regs_map_free(&cpqary3p->imr_handle);
787
		if (cpqary3p->ipq_handle)
788
			ddi_regs_map_free(&cpqary3p->ipq_handle);
789
		if (cpqary3p->opq_handle)
790
			ddi_regs_map_free(&cpqary3p->opq_handle);
791
		if (cpqary3p->ct_handle)
792
			ddi_regs_map_free(&cpqary3p->ct_handle);
793
	}
794

  
795
	if (status & CPQARY3_SOFTSTATE_ALLOC_DONE) {
796
		ddi_soft_state_free(cpqary3_state,
797
		    ddi_get_instance(cpqary3p->dip));
798
	}
799
}
800

  
801
/*
802
 * Function	: 	cpqary3_update_ctlrdetails
803
 * Description	: 	Performs Sanity check of the hw, Updates PCI Config
804
 *			Information, Verifies the supported board-id and
805
 *			Sets up a mapping for the Primary I2O Memory BAR and
806
 *			the Primary DRAM 1 BAR to access Host Interface
807
 *			registers and the Transport Configuration table.
808
 * Called By	: 	cpqary3_attach()
809
 * Parameters	: 	per-controller, bitmap (used for cleaning operations)
810
 * Return Values: 	SUCCESS / FAILURE
811
 *			[Success / failure depending upon the outcome of all
812
 *			checks and mapping. If any of them fail, a failure is
813
 *			sent back]
814
 */
815
static uint8_t
816
cpqary3_update_ctlrdetails(cpqary3_t *cpqary3p, uint32_t *cleanstatus)
817
{
818
	int8_t			retvalue;
819
	uint8_t			mem_bar0_set = 0;
820
	uint8_t			mem_64_bar0_set = 0;
821
	uint8_t			mem_bar1_set = 0;
822
	uint8_t			mem_64_bar1_set = 0;
823
	int32_t			reglen;
824
	uint32_t		*regp;
825
	uint32_t		mem_bar0 = 0;
826
	uint32_t		mem_64_bar0;
827
	uint32_t		mem_bar1 = 0;
828
	uint32_t		mem_64_bar1 = 0;
829
	uint32_t		ct_mem_bar = 0;
830
	uint32_t		ct_cfgmem_val = 0;
831
	uint32_t		ct_memoff_val = 0;
832
	uint32_t		ct_cfg_bar = 0;
833
	uint32_t		ct_mem_len = 0;
834
	offset_t		map_len = 0;
835
	uint32_t		regset_index;
836
	ddi_acc_handle_t 	pci_handle;
837
	uint32_t		*ct_cfg_offset;
838
	ddi_acc_handle_t	ct_cfgoff_handle;
839
	uint32_t		*ct_mem_offset;
840
	ddi_acc_handle_t	ct_memoff_handle;
841

  
842
	DBG("CPQary3: _update_ctlrdetails : Entering \n");
843

  
844
	RETURN_FAILURE_IF_NULL(cpqary3p);
845

  
846
	/*
847
	 * Check if the bus, or part of the bus  that  the  device  is installed
848
	 * on, permits the device to become a DMA master.
849
	 * If our device is not permitted to become master, return
850
	 */
851
	if (ddi_slaveonly(cpqary3p->dip) == DDI_SUCCESS)
852
		return (CPQARY3_FAILURE);
853

  
854
	/*
855
	 * Get the HW Configuration
856
	 * Get Bus #, Dev # and Func # for this device
857
	 * Free the memory that regp points towards after the
858
	 * ddi_getlongprop() call
859
	 */
860
	if (ddi_getlongprop(DDI_DEV_T_NONE, cpqary3p->dip, DDI_PROP_DONTPASS,
861
	    "reg", (caddr_t)&regp, &reglen) != DDI_PROP_SUCCESS)
862
		return (CPQARY3_FAILURE);
863

  
864
	cpqary3p->bus = PCI_REG_BUS_G(*regp);
865
	cpqary3p->dev = PCI_REG_DEV_G(*regp);
866
	cpqary3p->fun = PCI_REG_FUNC_G(*regp);
867

  
868
	for (regset_index = 0; regset_index < reglen / 20; regset_index ++) {
869
		if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x2) {
870
			if (!mem_bar0_set) {
871
				mem_bar0 = regset_index;
872
				mem_bar0_set = 1;
873
			} else if (!mem_bar1_set) {
874
				mem_bar1 = regset_index;
875
				mem_bar1_set = 1;
876
			}
877
		}
878
	}
879

  
880
	mem_64_bar0 = mem_bar0;
881
	mem_64_bar1 = mem_bar1;
882

  
883
	for (regset_index = 0; regset_index < reglen / 20; regset_index ++) {
884
		if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x3) {
885
			if (!mem_64_bar0_set) {
886
				mem_64_bar0 = regset_index;
887
				mem_64_bar0_set = 1;
888
			} else if (!mem_64_bar1_set) {
889
				mem_64_bar1 = regset_index;
890
				mem_64_bar1_set = 1;
891
			}
892
		}
893
	}
894

  
895
	mem_bar0 = mem_64_bar0;
896
	mem_bar1 = mem_64_bar1;
897

  
898
	MEM_SFREE(regp, reglen);
899

  
900
	/*
901
	 * Setup resources to access the Local PCI Bus
902
	 * If unsuccessful, return.
903
	 * Else, read the following from the PCI space:
904
	 * 	Sub-System Vendor ID
905
	 * 	Sub-System Device ID
906
	 * 	Interrupt Line
907
	 * 	Command Register
908
	 * Free the just allocated resources.
909
	 */
910
	if (pci_config_setup(cpqary3p->dip, &pci_handle) != DDI_SUCCESS)
911
		return (CPQARY3_FAILURE);
912

  
913
	cpqary3p->irq = pci_config_get8(pci_handle, PCI_CONF_ILINE);
914
	cpqary3p->board_id =
915
	    (pci_config_get16(pci_handle, PCI_CONF_SUBVENID) << 16)
916
	    | pci_config_get16(pci_handle, PCI_CONF_SUBSYSID);
917

  
918
	pci_config_teardown(&pci_handle);
919

  
920
	/*
921
	 * Verify Board Id
922
	 * If unsupported boards are detected, return.
923
	 * Update name for controller for driver use.
924
	 */
925
	cpqary3p->bddef = cpqary3_bd_getbybid(cpqary3p->board_id);
926
	if (cpqary3p->bddef == NULL) {
927
		cmn_err(CE_WARN,
928
		    "CPQary3: <Bid 0x%X> Controller NOT Supported",
929
		    cpqary3p->board_id);
930
		return (CPQARY3_FAILURE);
931
	}
932
	map_len = cpqary3p->bddef->bd_maplen;
933
	(void) strcpy(cpqary3p->hba_name, cpqary3p->bddef->bd_dispname);
934

  
935
	/*
936
	 * Set up a mapping for the following registers:
937
	 * 	Inbound Doorbell
938
	 * 	Outbound List Status
939
	 * 	Outbound Interrupt Mask
940
	 * 	Host Inbound Queue
941
	 * 	Host Outbound Queue
942
	 * 	Host Transport Configuration Table
943
	 * Mapping of the above has been done in that order.
944
	 */
945
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
946
	    mem_bar0, /* INDEX_PCI_BASE0, */
947
	    (caddr_t *)&cpqary3p->idr, (offset_t)I2O_IBDB_SET, map_len,
948
	    &cpqary3_dev_attributes, &cpqary3p->idr_handle);
949

  
950
	if (retvalue != DDI_SUCCESS) {
951
		if (DDI_REGS_ACC_CONFLICT == retvalue) {
952
			cmn_err(CE_WARN,
953
			    "CPQary3 : Registers Mapping Conflict");
954
		}
955
		cmn_err(CE_WARN, "CPQary3 : Inbound Doorbell "
956
		    "Register Mapping Failed");
957
		return (CPQARY3_FAILURE);
958
	}
959

  
960
	/* PERF */
961
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
962
	    mem_bar0, /* INDEX_PCI_BASE0, */
963
	    (caddr_t *)&cpqary3p->odr, (offset_t)I2O_OBDB_STATUS, map_len,
964
	    &cpqary3_dev_attributes, &cpqary3p->odr_handle);
965

  
966
	if (retvalue != DDI_SUCCESS) {
967
		if (DDI_REGS_ACC_CONFLICT == retvalue) {
968
			cmn_err(CE_WARN,
969
			    "CPQary3 : Registers Mapping Conflict");
970
		}
971
		cmn_err(CE_WARN,
972
		    "CPQary3 : Outbound Doorbell Register Mapping Failed");
973
		return (CPQARY3_FAILURE);
974
	}
975

  
976
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
977
	    mem_bar0, /* INDEX_PCI_BASE0, */
978
	    (caddr_t *)&cpqary3p->odr_cl, (offset_t)I2O_OBDB_CLEAR, map_len,
979
	    &cpqary3_dev_attributes, &cpqary3p->odr_cl_handle);
980

  
981
	if (retvalue != DDI_SUCCESS) {
982
		if (DDI_REGS_ACC_CONFLICT == retvalue) {
983
			cmn_err(CE_WARN,
984
			    "CPQary3 : Registers Mapping Conflict");
985
		}
986
		cmn_err(CE_WARN, "CPQary3 : Outbound Doorbell "
987
		    "Register Clear Mapping Failed");
988
		return (CPQARY3_FAILURE);
989
	}
990

  
991
	/* LOCKUP CODE */
992
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
993
	    mem_bar0, /* INDEX_PCI_BASE0, */
994
	    (caddr_t *)&cpqary3p->spr0, (offset_t)I2O_CTLR_INIT, map_len,
995
	    &cpqary3_dev_attributes, &cpqary3p->spr0_handle);
996

  
997
	if (retvalue != DDI_SUCCESS) {
998
		if (DDI_REGS_ACC_CONFLICT == retvalue) {
999
			cmn_err(CE_WARN,
1000
			    "CPQary3 : Registers Mapping Conflict");
1001
		}
1002
		cmn_err(CE_WARN,
1003
		    "CPQary3 : Scratch Pad register zero Mapping Failed");
1004
		return (CPQARY3_FAILURE);
1005
	}
1006
	/* LOCKUP CODE */
1007
	/* PERF */
1008

  
1009
	*cleanstatus |= CPQARY3_MEM_MAPPED;
1010

  
1011
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1012
	    mem_bar0, /* INDEX_PCI_BASE0, */
1013
	    (caddr_t *)&cpqary3p->isr, (offset_t)I2O_INT_STATUS, map_len,
1014
	    &cpqary3_dev_attributes, &cpqary3p->isr_handle);
1015

  
1016
	if (retvalue != DDI_SUCCESS) {
1017
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1018
			cmn_err(CE_WARN,
1019
			    "CPQary3 : Registers Mapping Conflict");
1020
		}
1021
		cmn_err(CE_WARN,
1022
		    "CPQary3 : Interrupt Status Register Mapping Failed");
1023
		return (CPQARY3_FAILURE);
1024
	}
1025

  
1026
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1027
	    mem_bar0, /* INDEX_PCI_BASE0, */
1028
	    (caddr_t *)&cpqary3p->imr, (offset_t)I2O_INT_MASK, map_len,
1029
	    &cpqary3_dev_attributes, &cpqary3p->imr_handle);
1030

  
1031
	if (retvalue != DDI_SUCCESS) {
1032
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1033
			cmn_err(CE_WARN,
1034
			    "CPQary3 : Registers Mapping Conflict");
1035
		}
1036
		cmn_err(CE_WARN,
1037
		    "CPQary3 : Interrupt Mask Register Mapping Failed");
1038
		return (CPQARY3_FAILURE);
1039
	}
1040

  
1041
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1042
	    mem_bar0, /* INDEX_PCI_BASE0, */
1043
	    (caddr_t *)&cpqary3p->ipq, (offset_t)I2O_IBPOST_Q, map_len,
1044
	    &cpqary3_dev_attributes, &cpqary3p->ipq_handle);
1045

  
1046
	if (retvalue != DDI_SUCCESS) {
1047
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1048
			cmn_err(CE_WARN,
1049
			    "CPQary3 : Registers Mapping Conflict");
1050
		}
1051
		cmn_err(CE_WARN,
1052
		    "CPQary3 : Inbound Queue Register Mapping Failed");
1053
		return (CPQARY3_FAILURE);
1054
	}
1055

  
1056
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1057
	    mem_bar0, /* INDEX_PCI_BASE0, */ (caddr_t *)&cpqary3p->opq,
1058
	    (offset_t)I2O_OBPOST_Q, map_len, &cpqary3_dev_attributes,
1059
	    &cpqary3p->opq_handle);
1060

  
1061
	if (retvalue != DDI_SUCCESS) {
1062
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1063
			cmn_err(CE_WARN,
1064
			    "CPQary3 : Registers Mapping Conflict");
1065
		}
1066
		cmn_err(CE_WARN, "CPQary3 : Outbound Post Queue "
1067
		    "Register Mapping Failed");
1068
		return (CPQARY3_FAILURE);
1069
	}
1070

  
1071

  
1072
	/*
1073
	 * The config offset and memory offset have to be obtained in order to
1074
	 * locate the config table.
1075
	 */
1076
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1077
	    mem_bar0, /* INDEX_PCI_BASE0, */ (caddr_t *)&ct_cfg_offset,
1078
	    (offset_t)CT_CFG_OFFSET, map_len, &cpqary3_dev_attributes,
1079
	    &ct_cfgoff_handle);
1080

  
1081
	if (retvalue != DDI_SUCCESS) {
1082
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1083
			cmn_err(CE_WARN,
1084
			    "CPQary3 : Registers Mapping Conflict");
1085
		}
1086
		cmn_err(CE_WARN, "CPQary3 : Configuration Table "
1087
		    "Register Mapping Failed");
1088
		return (CPQARY3_FAILURE);
1089
	}
1090

  
1091
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1092
	    mem_bar0, /* INDEX_PCI_BASE0, */
1093
	    (caddr_t *)&ct_mem_offset, (offset_t)CT_MEM_OFFSET, map_len,
1094
	    &cpqary3_dev_attributes, &ct_memoff_handle);
1095

  
1096
	if (retvalue != DDI_SUCCESS) {
1097
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1098
			cmn_err(CE_WARN,
1099
			    "CPQary3 : Registers Mapping Conflict");
1100
		}
1101
		cmn_err(CE_WARN, "CPQary3 : Configuration Table "
1102
		    "Register Mapping Failed");
1103
		return (CPQARY3_FAILURE);
1104
	}
1105

  
1106
	ct_cfgmem_val = (uint32_t)ddi_get32(ct_cfgoff_handle, ct_cfg_offset);
1107
	ct_memoff_val = (uint32_t)ddi_get32(ct_memoff_handle, ct_mem_offset);
1108

  
1109
	ddi_regs_map_free(&ct_cfgoff_handle);
1110
	ddi_regs_map_free(&ct_memoff_handle);
1111

  
1112
	ct_cfg_bar = (ct_cfgmem_val & 0x0000ffff);
1113
	ct_mem_len = (ct_cfgmem_val & 0xffff0000);
1114
	ct_mem_len = (ct_mem_len >> 16);
1115

  
1116
	if (ct_cfg_bar == 0x10) {
1117
		if (ct_mem_len) {
1118
			ct_mem_bar = mem_64_bar0;
1119
		} else {
1120
			ct_mem_bar = mem_bar0;
1121
		}
1122

  
1123
	} else if (ct_cfg_bar == 0x14) {
1124
		if (ct_mem_len) {
1125
			ct_mem_bar = mem_64_bar1;
1126
		} else {
1127
			ct_mem_bar = mem_bar1;
1128
		}
1129
	} else {
1130
		return (CPQARY3_FAILURE);
1131
	}
1132

  
1133

  
1134
	/*
1135
	 * The Configuration Table(CT) shall be mapped in the form of a
1136
	 * structure since several members in the CT need to be accessed
1137
	 * to read and write.
1138
	 */
1139
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1140
	    ct_mem_bar, /* INDEX_PCI_BASE0/1, */
1141
	    (caddr_t *)&cpqary3p->ct, (offset_t)ct_memoff_val,
1142
	    sizeof (CfgTable_t), &cpqary3_dev_attributes, &cpqary3p->ct_handle);
1143

  
1144
	if (retvalue != DDI_SUCCESS) {
1145
		if (retvalue == DDI_REGS_ACC_CONFLICT) {
1146
			cmn_err(CE_WARN,
1147
			    "CPQary3 : Registers Mapping Conflict");
1148
		}
1149
		cmn_err(CE_WARN, "CPQary3 : Configuration Table "
1150
		    "Register Mapping Failed");
1151
		return (CPQARY3_FAILURE);
1152
	}
1153

  
1154
	/* PERF */
1155

  
1156
	retvalue = ddi_regs_map_setup(cpqary3p->dip,
1157
	    ct_mem_bar, /* INDEX_PCI_BASE0/1, */
1158
	    (caddr_t *)&cpqary3p->cp,
1159
	    (offset_t)(ct_memoff_val + cpqary3p->ct->TransportMethodOffset),
1160
	    sizeof (CfgTrans_Perf_t), &cpqary3_dev_attributes,
1161
	    &cpqary3p->cp_handle);
1162

  
1163
	if (retvalue != DDI_SUCCESS) {
1164
		if (retvalue == DDI_REGS_ACC_CONFLICT)
1165
			cmn_err(CE_WARN,
1166
			    "CPQary3 : Registers Mapping Conflict");
1167
		cmn_err(CE_WARN, "CPQary3 : Performant Transport Method Table "
1168
		    "Mapping Failed");
1169
		return (CPQARY3_FAILURE);
1170
	}
1171

  
1172
	/* PERF */
1173

  
1174
	DBG("CPQary3 : _update_ctlrdetails : Leaving \n");
1175

  
1176
	return (CPQARY3_SUCCESS);
1177
}
......
0
-- /dev/null	Wed Aug 28 00:24:39 2013
1178
++ new/usr/src/uts/common/io/cpqary3/cpqary3.conf	Wed Aug 28 00:24:39 2013
......
1
#
2
# This file and its contents are supplied under the terms of the
3
# Common Development and Distribution License ("CDDL"), version 1.0.
4
# You may only use this file in accordance with the terms of version
5
# 1.0 of the CDDL.
6
#
7
# A full copy of the text of the CDDL should have accompanied this
8
# source.  A copy of the CDDL is also available via the Internet at
9
# http://www.illumos.org/license/CDDL.
10
#
11

  
12
#
13
#   Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
14
#
15

  
16
# There are one configurable parameters in the CPQary3 driver
17
# for supporting tapes.
18

  
19
tape="sctp";
20
scsi-no-quiesce=1;
21
cpqary3_noesupport="off";
......
0
-- /dev/null	Wed Aug 28 00:24:39 2013
22
++ new/usr/src/uts/common/io/cpqary3/cpqary3.h	Wed Aug 28 00:24:39 2013
......
1
/*
2
 * This file and its contents are supplied under the terms of the
3
 * Common Development and Distribution License ("CDDL"), version 1.0.
4
 * You may only use this file in accordance with the terms of version
5
 * 1.0 of the CDDL.
6
 *
7
 * A full copy of the text of the CDDL should have accompanied this
8
 * source.  A copy of the CDDL is also available via the Internet at
9
 * http://www.illumos.org/license/CDDL.
10
 */
11

  
12
/*
13
 * Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
14
 */
15

  
16
#ifndef	_CPQARY3_H
17
#define	_CPQARY3_H
18

  
19
#include <sys/types.h>
20
#include <sys/pci.h>
21
#include <sys/param.h>
22
#include <sys/errno.h>
23
#include <sys/conf.h>
24
#include <sys/map.h>
25
#include <sys/modctl.h>
26
#include <sys/kmem.h>
27
#include <sys/cmn_err.h>
28
#include <sys/stat.h>
29
#include <sys/scsi/scsi.h>
30
#include <sys/devops.h>
31
#include <sys/ddi.h>
32
#include <sys/sunddi.h>
33

  
34
#include <cpqary3_ciss.h>
35
#include <cpqary3_bd.h>
36

  
37
#ifdef	__cplusplus
38
extern "C" {
39
#endif
40

  
41
/* #define CPQARY3_DBG */
42

  
43
#if defined(CPQARY3_DBG) || defined(lint)
44
#define	DBG(x)			cmn_err(CE_CONT, x)
45
#else
46
#define	DBG(x)
47
#endif
48

  
... This diff was truncated because it exceeds the maximum size that can be displayed.
    (1-1/1)