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Feature #11367

closed

Capture PCI Express width and speed

Added by Robert Mustacchi about 3 years ago. Updated about 3 years ago.

Status:
Closed
Priority:
Normal
Category:
kernel
Start date:
Due date:
% Done:

100%

Estimated time:
Difficulty:
Medium
Tags:
Gerrit CR:
External Bug:

Description

There's no great way today to get the current running speed of a given PCIe device with respect to its capable speeds and currently running speed. e.g. I put an x1 device in an x16 slot.

An example in action:

> ::prtconf -d i40e | ::print struct dev_info devi_bus.port_up.priv_p | ::print pcie_bus_t
{
    bus_dip = 0xffffff03e1257b10
    bus_rp_dip = 0xffffff03e125c088
    bus_cfg_hdl = 0xffffff03e8389040
    bus_fm_flags = 0x1
    bus_soft_state = 0
    bus_bdf = 0x100
    bus_rp_bdf = 0x8
    bus_dev_ven_id = 0x158b8086
    bus_rev_id = 0x2
    bus_hdr_type = 0
    bus_dev_type = 0
    bus_bdg_secbus = 0
    bus_pcie_off = 0xa0
    bus_aer_off = 0x100
    bus_pcix_off = 0
    bus_pci_hp_off = 0
    bus_ecc_ver = 0
    bus_bus_range = {
        lo = 0
        hi = 0
    }
    bus_addr_ranges = 0
    bus_addr_entries = 0
    bus_assigned_addr = 0xffffff03e39ba500
    bus_assigned_entries = 0x2
    bus_pfd = 0xffffff03e27756a0
    bus_dom = 0xffffff03e7b85648
    bus_mps = 0x1
    bus_plat_private = 0xffffff03e3ad40f8
    bus_hp_sup_modes = 0 (0)
    bus_hp_curr_mode = 0 (0)
    bus_hp_ctrl = 0
    bus_ari = 0
    bus_cfgacc_base = 0
    bus_pcie2pci_secbus = 0
    bus_max_width = 4 (PCIE_LINK_WIDTH_X8)
    bus_cur_width = 4 (PCIE_LINK_WIDTH_X8)
    bus_sup_speed = 0x7 (PCIE_LINK_SPEED_{2_5|5|8})
    bus_max_speed = 0x4 (PCIE_LINK_SPEED_8)
    bus_cur_speed = 0x4 (PCIE_LINK_SPEED_8)
}
{
    bus_dip = 0xffffff03e1257850
    bus_rp_dip = 0xffffff03e125c088
    bus_cfg_hdl = 0xffffff03e4d91880
    bus_fm_flags = 0x1
    bus_soft_state = 0
    bus_bdf = 0x101
    bus_rp_bdf = 0x8
    bus_dev_ven_id = 0x158b8086
    bus_rev_id = 0x2
    bus_hdr_type = 0
    bus_dev_type = 0
    bus_bdg_secbus = 0
    bus_pcie_off = 0xa0
    bus_aer_off = 0x100
    bus_pcix_off = 0
    bus_pci_hp_off = 0
    bus_ecc_ver = 0                   
    bus_bus_range = {
        lo = 0
        hi = 0
    }
    bus_addr_ranges = 0
    bus_addr_entries = 0
    bus_assigned_addr = 0xffffff03e39ba540
    bus_assigned_entries = 0x2
    bus_pfd = 0xffffff03e2775628
    bus_dom = 0xffffff03e7087198
    bus_mps = 0x1
    bus_plat_private = 0xffffff03e3ad4080
    bus_hp_sup_modes = 0 (0)
    bus_hp_curr_mode = 0 (0)
    bus_hp_ctrl = 0
    bus_ari = 0
    bus_cfgacc_base = 0
    bus_pcie2pci_secbus = 0
    bus_max_width = 4 (PCIE_LINK_WIDTH_X8)
    bus_cur_width = 4 (PCIE_LINK_WIDTH_X8)
    bus_sup_speed = 0x7 (PCIE_LINK_SPEED_{2_5|5|8})
    bus_max_speed = 0x4 (PCIE_LINK_SPEED_8)
    bus_cur_speed = 0x4 (PCIE_LINK_SPEED_8)
}
Actions #1

Updated by Electric Monk about 3 years ago

  • Status changed from New to Closed

git commit 662dc8a578c4b6decf73ecc776c43128bac8dc83

commit  662dc8a578c4b6decf73ecc776c43128bac8dc83
Author: Robert Mustacchi <rm@joyent.com>
Date:   2019-08-19T17:40:33.000Z

    11367 Capture PCI Express width and speed
    Reviewed by: Dan McDonald <danmcd@joyent.com>
    Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
    Reviewed by: Toomas Soome <tsoome@me.com>
    Reviewed by: Paul Winder <Paul.Winder@wdc.com>
    Approved by: Richard Lowe <richlowe@richlowe.net>

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