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Bug #12304

risc-v dis instruction alignment too restrictive

Added by Robert Mustacchi about 2 months ago. Updated 27 days ago.

Status:
Closed
Priority:
Normal
Category:
lib - userland libraries
Start date:
Due date:
% Done:

100%

Estimated time:
Difficulty:
Medium
Tags:

Description

While reviewing the risc-v ISA docs, I discovered that I mistakenly over-restricted the alignment of instructions in dis. In particular, when using the compressed instruction set, the alignment of 32-bit instructions is in fact allowed to be 16-bit aligned and does not require 32-bit alignment. We should reduce this restriction in dis.

History

#1

Updated by Robert Mustacchi about 1 month ago

I tested this by running the dis test suite for RISC-V:

rm@turin:/ws/rm/dis/usr/src/test/util-tests/tests/dis$ LD_PRELOAD_32=/usr/lib/libdisasm.so.1 ksh distest.ksh -n -p risc-v=/ws/rm/binutils-2.31/gas/as-new
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.pseudo.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.pseudo.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.csr.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.csr.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32d.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32d.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32f.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32f.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32m.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32m.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32i.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32i.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.fpregs.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.fpregs.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.supervisor.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.supervisor.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.regs.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.regs.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32a.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/tst.rv32a.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/64.rv64i.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/64.rv64a.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/64.rv64d.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/64.rv64m.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v/64.rv64f.s ... passed

--------------
libdis Results
--------------

Tests passed: 25
Tests failed: 0
Tests ran:    25
rm@turin:/ws/rm/dis/usr/src/test/util-tests/tests/dis$ LD_PRELOAD_32=/usr/lib/libdisasm.so.1 ksh distest.ksh -n -p risc-v-c=/ws/rm/binutils-2.31/gas/as-new
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/tst.int.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/tst.int.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/tst.ldsr.s (32-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/tst.ldsr.s (64-bit) ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/32.ldsr.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/64.int.s ... passed
testing /ws/rm/dis/usr/src/test/util-tests/tests/dis/risc-v-c/64.ldsr.s ... passed

--------------
libdis Results
--------------

Tests passed: 7
Tests failed: 0
Tests ran:    7
#2

Updated by Electric Monk 27 days ago

  • Status changed from New to Closed
  • % Done changed from 90 to 100

git commit 388488112189b484c639b410a453c22e93bdfb68

commit  388488112189b484c639b410a453c22e93bdfb68
Author: Robert Mustacchi <rm@fingolfin.org>
Date:   2020-03-07T09:36:20.000Z

    12304 risc-v dis instruction alignment too restrictive
    Reviewed by: Andy Fiddaman <andy@omniosce.org>
    Reviewed by: Jason King <jason.king@joyent.com>
    Approved by: Dan McDonald <danmcd@joyent.com>

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