Bug #12751

Update the cached MSI state when any MSI capability register is written.

Added by Michael Zeller 6 months ago. Updated 6 months ago.

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We should pull in the following bhyve commit from FreeBSD.
Bhyve users on FreeBSD have reported that Ubuntu 20.04 fails to install due to this bug.
On SmartOS I have seen what seems to be a correlation between this commit and a segv in bhyve in umouse_request() .
I plan on opening a follow up ticket for hardening umouse_request() .

commit e8a9ef1b0e1d34627019fc409471f6482b14f169
Author:     jhb <>
AuthorDate: Mon Apr 27 22:27:35 2020 +0000
Commit:     jhb <>
CommitDate: Mon Apr 27 22:27:35 2020 +0000

    Update the cached MSI state when any MSI capability register is written.

    bhyve uses cached copies of the MSI capability registers to generate
    MSI interrupts for device models.  Previously, these cached fields
    were only set when the MSI capability control register was updated.
    The Linux kernel recently adopted a change to deal with races in MSI
    interrupt delivery that writes to the MSI capability address and data
    registers to alter the destination of MSI interrupts without writing
    to the MSI capability control register.  bhyve was not updating its
    cached registers for these writes and continued to send interrupts
    with the old data value to the old address.  Fix this by recomputing
    the cached values for every write to any MSI capability register.

    Reported by:    Jason Tubnor, Ryan Moeller
    Reported by:    Marc Dionne (bisected the Linux kernel commit)
    Reviewed by:    grehan
    MFC after:      1 week
    Differential Revision:

 usr.sbin/bhyve/pci_emul.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

Related issues

Related to illumos gate - Feature #12792: bhyve upstream sync 2020 MayClosedPatrick Mooney


Updated by Patrick Mooney 6 months ago


Updated by Patrick Mooney 6 months ago

  • Status changed from New to Resolved

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