Project

General

Profile

Bug #12956

bhyve should set TMR on intr accept

Added by Patrick Mooney 26 days ago. Updated 26 days ago.

Status:
New
Priority:
Normal
Category:
bhyve
Start date:
Due date:
% Done:

0%

Estimated time:
Difficulty:
Medium
Tags:
Gerrit CR:

Description

Currently, bhyve manages the contents of trigger mode registers (TMRs) in the vlapic based on the state of interrupt mappings in the ioapic. This is at odd with the architectural definition of that state:

The trigger mode register (TMR) indicates the trigger mode of the interrupt (see Figure 10-20). Upon acceptance of an interrupt into the IRR, the corresponding TMR bit is cleared for edge-triggered interrupts and set for level-triggered interrupts. If a TMR bit is set when an EOI cycle for its corresponding interrupt vector is generated, an EOI message is sent to all I/O APICs.

The existing model was likely expedient at the time, especially in the face of how APICv/posted-interrupts were implemented. For the sake of an implementation that more closely matched architectural expectations, it would be nice if we did the proper thing here.

History

#1

Updated by Patrick Mooney 26 days ago

See also: OS-7622 bhyve vioapic writes can deadlock instance

Also available in: Atom PDF