illumos gate

According to the IA-PC HPET Specification 1.0a the Timer N Configuration and Capability Register is always 64-bits in size. The upper 32-bits represents a single read-only field, Tn_INT_ROUTE_CAP, which contains the map of valid I/O APIC interrupts to which this timer may be routed.

The configuration also contains a bit that informs us whether the timer value is a 32-bit or 64-bit value, Tn_SIZE_CAP. Unfortunately we have conflated the timer value size with the width of the configuration register:

static void
hpet_write_timer_N_config(hpet_info_t *hip, uint_t n, uint64_t l)
{
        if (hip->timer_n_config[n].size_cap == 1)
                *(uint64_t *)HPET_TIMER_N_CONF_ADDRESS(
                    hip->logical_address, n) = l;
        else
                *(uint32_t *)HPET_TIMER_N_CONF_ADDRESS(
                    hip->logical_address, n) = (uint32_t)(0xFFFFFFFF & l);
}

This is not quite right, though fortunately in a way that has been effectively benign; the upper half of the register is read-only anyway and never needs to be written. We should nonetheless correct this oversight.