Bug #13440

ppin disablement path missing state transition

Added by Robert Mustacchi 3 months ago. Updated 3 months ago.

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Due date:
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Upon recently reviewing the AMD specific MSRs for PPIN, they make something more explicit, which Intel makes more subtle. Which is that the path for disabling and locking the PPIN MSR needs to be done in two steps, as opposed to a single one that disables and locks it. Dan saw this tripped over on a system which we found because for an unrelated reason, the on_trap/no_trap failed and resulted in a double fault.

We were able to verify that by doing this in two steps, we no longer triggered the #GP on the MSR and Dan's system were booting fine.


Updated by Electric Monk 3 months ago

  • Gerrit CR set to 1159

Updated by Dan McDonald 3 months ago

Discovered on an AMD EPYC 7402P system from Dell. Did not have easy access to BIOS and BIOS settings, but the initial double-fault I saw was reproducible, and the GP that was the first fault went away with this fix.

Anyone who uses Equinix Metal with illumos should know that this bug will enable the use c3.medium.x86 systems.


Updated by Robert Mustacchi 3 months ago

I also verified that everything worked correctly on an AsRock Rack EPYC 7282 special.


Updated by Electric Monk 3 months ago

  • Status changed from New to Closed
  • % Done changed from 0 to 100

git commit abe1d126b4a1229ee2861d65508e7a52bd8c2721

commit  abe1d126b4a1229ee2861d65508e7a52bd8c2721
Author: Robert Mustacchi <>
Date:   2021-01-12T22:02:42.000Z

    13440 ppin disablement path missing state transition
    Reviewed by: Richard Lowe <>
    Reviewed by: Dan McDonald <>
    Reviewed by: Patrick Mooney <>
    Approved by: Gordon Ross <>

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