ppin disablement path missing state transition
Upon recently reviewing the AMD specific MSRs for PPIN, they make something more explicit, which Intel makes more subtle. Which is that the path for disabling and locking the PPIN MSR needs to be done in two steps, as opposed to a single one that disables and locks it. Dan saw this tripped over on a system which we found because for an unrelated reason, the
no_trap failed and resulted in a double fault.
We were able to verify that by doing this in two steps, we no longer triggered the #GP on the MSR and Dan's system were booting fine.
Updated by Dan McDonald 3 months ago
Discovered on an AMD EPYC 7402P system from Dell. Did not have easy access to BIOS and BIOS settings, but the initial double-fault I saw was reproducible, and the GP that was the first fault went away with this fix.
Anyone who uses Equinix Metal with illumos should know that this bug will enable the use c3.medium.x86 systems.
Updated by Electric Monk 3 months ago
- Status changed from New to Closed
- % Done changed from 0 to 100
commit abe1d126b4a1229ee2861d65508e7a52bd8c2721 Author: Robert Mustacchi <firstname.lastname@example.org> Date: 2021-01-12T22:02:42.000Z 13440 ppin disablement path missing state transition Reviewed by: Richard Lowe <email@example.com> Reviewed by: Dan McDonald <firstname.lastname@example.org> Reviewed by: Patrick Mooney <email@example.com> Approved by: Gordon Ross <firstname.lastname@example.org>