ppin disablement path missing state transition
Upon recently reviewing the AMD specific MSRs for PPIN, they make something more explicit, which Intel makes more subtle. Which is that the path for disabling and locking the PPIN MSR needs to be done in two steps, as opposed to a single one that disables and locks it. Dan saw this tripped over on a system which we found because for an unrelated reason, the
no_trap failed and resulted in a double fault.
We were able to verify that by doing this in two steps, we no longer triggered the #GP on the MSR and Dan's system were booting fine.