Bug #14101
closed
bhyve should expose shadowed bits in CRs
100%
Description
The VMX side of bhyve requires shadowing certain bits in %cr0 and %cr4, since they are required to be 0 or 1, regardless of the guest's intent. The VMCS has fields from which the shadowed bits can be read, but the bhyve interfaces which expose register state to userspace (or the rest of the in-kernel emulation) fail to take them into account. While other emulation is not likely interested in shadowed bits such as CR0.CD, it would be good to properly integrate them into the get-register output so they match the state observed by the guest.
Related issues
Updated by Patrick Mooney over 1 year ago
- Related to Bug #14100: bhyve misses TLB flush for shadowed cr0 added
Updated by Patrick Mooney over 1 year ago
It should be noted that the SVM logic for this properly handles the shadowed bits in %cr0 (and does not shadow %cr4)
Updated by Patrick Mooney over 1 year ago
Prior to putting the fix in place, shadowed bits are not reflected in values queried from cr0 (and cr4):
root@ferrata:~# bhyvectl --create --vm=testvm
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000000000000
root@ferrata:~# # bhyvectl expects decimal values to set register state
root@ferrata:~# mdb -e '80050013=E'
2147811347
root@ferrata:~# bhyvectl --vm=testvm --set-cr0=2147811347
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000080050033
root@ferrata:~# mdb -e 'c0050013=E'
3221553171
root@ferrata:~# bhyvectl --vm=testvm --set-cr0=3221553171
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000080050033
Updated by Patrick Mooney over 1 year ago
With the proposed fix in place, changes to cr0 which effect the shadowed bits are observable when reading the value back out:
root@ferrata:~# bhyvectl --create --vm=testvm
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000060000000
root@ferrata:~# bhyvectl --vm=testvm --set-cr0=2147811347
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000080050013
root@ferrata:~# mdb -e 'c0050013=E'
3221553171
root@ferrata:~# bhyvectl --vm=testvm --set-cr0=3221553171
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x00000000c0050013
root@ferrata:~# bhyvectl --vm=testvm --set-cr0=0
root@ferrata:~# bhyvectl --vm=testvm --get-cr0
cr0[0] 0x0000000000000000
root@ferrata:~# bhyvectl --vm=testvm --get-cr4
cr4[0] 0x0000000000000000
root@ferrata:~# bhyvectl --vm=testvm --set-cr4=8192
root@ferrata:~# bhyvectl --vm=testvm --get-cr4
cr4[0] 0x0000000000002000
Updated by Electric Monk over 1 year ago
- Status changed from In Progress to Closed
- % Done changed from 80 to 100
git commit bf0dcd3f9893153e708295693e9015919b00112b
commit bf0dcd3f9893153e708295693e9015919b00112b
Author: Patrick Mooney <pmooney@pfmooney.com>
Date: 2021-09-27T19:48:33.000Z
14100 bhyve misses TLB flush for shadowed cr0
14101 bhyve should expose shadowed bits in CRs
Reviewed by: Andy Fiddaman <andy@omnios.org>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@joyent.com>