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Bug #14734
closed
pcieadm decodes expansion ROM address incorrectly
Start date:
Due date:
% Done:
100%
Estimated time:
Difficulty:
Bite-size
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Gerrit CR:
External Bug:
Description
The expansion ROM BAR is defined such that bits [31:11] contain bits [31:11] of the ROM address, so that a register containing 0xa8180001 would describe an enabled ROM decode for addresses starting from 0xa8180000; if the last bit were instead 0 the address would have the same meaning but the BAR would be disabled. Instead we see:
Expansion ROM: 0xa8180000
|--> Enable: disabled (0x0)
|--> Base Address: 0x2a060000000
This is because we're taking [31:11] as an integer and then shifting it left 21 in pcieadm_regdef_exprom. We need only shift it left 11.
Updated by Robert Mustacchi over 1 year ago
I fixed this and added the recent fields that were in the PCIe gen 5 spec here. With this fixed here's what you now see:
$ for f in *.pci; do ../pcieadm show-cfgspace -f $f header0.rom; done
...
Device c1-00-00.pci -- Type 0 Header
Expansion ROM: 0x96800000
|--> Enable: disabled (0x0)
|--> Validation Status: not supported (0x0)
|--> Validation Details: 0x0
|--> Base Address: 0x96800000
Device c1-00-01.pci -- Type 0 Header
Expansion ROM: 0x96680000
|--> Enable: disabled (0x0)
|--> Validation Status: not supported (0x0)
|--> Validation Details: 0x0
|--> Base Address: 0x96680000
Device c1-00-02.pci -- Type 0 Header
Expansion ROM: 0x96500000
|--> Enable: disabled (0x0)
|--> Validation Status: not supported (0x0)
|--> Validation Details: 0x0
|--> Base Address: 0x96500000
Updated by Electric Monk over 1 year ago
- Status changed from New to Closed
- % Done changed from 0 to 100
git commit 6c489a5260bcb010bd6a712e312b0aa29cd591b8
commit 6c489a5260bcb010bd6a712e312b0aa29cd591b8
Author: Robert Mustacchi <rm@fingolfin.org>
Date: 2022-07-13T13:53:32.000Z
14734 pcieadm decodes expansion ROM address incorrectly
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Andy Fiddaman <andy@omnios.org>
Approved by: Garrett D'Amore <garrett@damore.org>
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