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Feature #14835

closed

split cpuid pass1

Added by Robert Mustacchi 3 months ago. Updated about 2 months ago.

Status:
Closed
Priority:
Normal
Category:
kernel
Start date:
Due date:
% Done:

100%

Estimated time:
Difficulty:
Medium
Tags:
Gerrit CR:
External Bug:

Description

This goes with #14834. Ignoring entirely where and how these steps are implemented, on any modern x86 processor the following four steps have to be executed in order on each CPU (thread/AP/etc):

  1. Fetch the brand string from somewhere and program it so that cpuid can read it. This may be fixed on Intel CPUs; on AMD CPUs it's normally read from the SMU although in principle it could come from anywhere.
  1. Use standard architectural cpuid executions to get our make/model/revision/socket, and optionally compute derived bits like chiprev where applicable. In general this doesn't rely on the brand string but this is the obvious opportunity to save that as well.
  2. Set up various non-architectural MSRs that control exposure of features via architectural cpuid instructions. Both the features to be exposed and the means of controlling their exposure may depend on arbitrarily fine-grained processor identity discovered in the previous step.
  3. Use standard architectural cpuid executions to extract all the feature bits we care about, optionally masking off those we know or believe to be broken or that have been forbidden by operator-defined policy.

Steps 2 and 4 are done in (with #14834 ) ISA-dep code, currently cpuid_pass1(). On i86pc, steps 1 and 3 are done by firmware prior to boot; obviously firmware also does enough of step 2 to understand how to perform step 3, but we still have to do that again ourselves as the information retrieved by firmware isn't usefully available to us. On oxide, steps 1 and 3 are done by machdep OS code.

To accommodate this, we split cpuid pass 1 into a new pass 0 responsible solely for basic identifying information and the remainder of pass 1 which is responsible for most of the feature bits as it is today. This allows us to execute the 4 required steps in the proper sequence without needing to make any of the code that does steps 2 and 4 machine-specific. Doing this requires only very minimal changes to i86pc and ISA-dep code, making this another candidate for immediate upstream integration.

~~~

Note, as part of this we opted to rename the passes to make them both easier to understand, reason about what they were doing, and make it easier to make future changes to the ordering of them.


Related issues

Related to illumos gate - Feature #14834: cpuid code is and has always been isadepClosedRobert Mustacchi

Actions
Related to illumos gate - Feature #14836: extend AMD chiprev mechanism to identify core revsClosedRobert Mustacchi

Actions
Actions #1

Updated by Robert Mustacchi 3 months ago

  • Related to Feature #14834: cpuid code is and has always been isadep added
Actions #2

Updated by Robert Mustacchi 3 months ago

  • Related to Feature #14836: extend AMD chiprev mechanism to identify core revs added
Actions #3

Updated by Electric Monk 3 months ago

  • Gerrit CR set to 2254
Actions #4

Updated by Robert Mustacchi about 2 months ago

This was all tested alongside #14834. Please see that for testing notes.

Actions #5

Updated by Electric Monk about 2 months ago

  • Status changed from New to Closed
  • % Done changed from 0 to 100

git commit ab5bb018eb284290d89d61bbae1913c3ea82b3af

commit  ab5bb018eb284290d89d61bbae1913c3ea82b3af
Author: Keith M Wesolowski <wesolows@oxide.computer>
Date:   2022-08-20T18:04:45.000Z

    14834 cpuid code is and has always been isadep
    14835 split cpuid pass1
    Reviewed by: Robert Mustacchi <rm@fingolfin.org>
    Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
    Approved by: Garrett D'Amore <garrett@damore.org>

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