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Feature #14893

closed

pcieadm 32.0 GT/s physical layer capability decoding

Added by Robert Mustacchi about 2 months ago. Updated about 2 months ago.

Status:
Closed
Priority:
Normal
Category:
cmd - userland programs
Start date:
Due date:
% Done:

100%

Estimated time:
Difficulty:
Medium
Tags:
Gerrit CR:
External Bug:

Description

With the advent of PCIe Gen 5 coming to platforms, we should extend pcieadm to cover the 32.0 GT/s physical layer information. Here are two example of what this looks like against actual systems:

$ ./pcieadm show-cfgspace -f ~/pci/c4-00-00.pci pl32g
Physical Layer 32.0 GT/s Capability (0x2a)
  Capability Header: 0x1002a
    |--> Capability ID: 0x2a
    |--> Capability Version: 0x1
    |--> Next Capability Offset: 0x0
  32.0 GT/s Capabilities: 0x101
    |--> Equalization Bypass to Highest NRZ Rate: supported (0x1)
    |--> No Equalization Needed: unsupported (0x0)
    |--> Modified TS Usage Mode 0 - PCI Express: supported (0x100)
    |--> Modified TS Usage Mode 1 - Training Set Message: unsupported (0x0)
    |--> Modified TS Usage Mode 2 - Alternate Protocol: unsupported (0x0)
  32.0 GT/s Control: 0x0
    |--> Equalization Bypass to Highest NRZ Rate: enabled (0x0)
    |--> No Equalization Needed: enabled (0x0)
    |--> Modified TS Usage Mode Selected: PCIe (0x0)
  32.0 GT/s Status: 0x4f
    |--> Equalization 32.0 GT/s Complete: complete (0x1)
    |--> Equalization 32.0 GT/s Phase 1: successful (0x2)
    |--> Equalization 32.0 GT/s Phase 2: successful (0x4)
    |--> Equalization 32.0 GT/s Phase 3: successful (0x8)
    |--> Link Equalization Request 32.0 GT/s: 0x0
    |--> Modified TS Received: no (0x0)
    |--> Received Enhanced Link Behavior Control: equalization bypass to highest rate (0x40)
    |--> Transmitter Precoding: disabled (0x0)
    |--> Transmitter Precoding Request: disabled (0x0)
    |--> No Equalization Needed Received: no (0x0)
  Received Modified TS Data 1: 0x0
    |--> Modified TS Usage Mode Selected: PCIe (0x0)
    |--> Received Modified TS Information 1: 0x0
    |--> Received Modified TS Vendor ID: 0x0
  Received Modified TS Data 2: 0x0
    |--> Received Modified TS Information 2: 0x0
    |--> Alternate Protocol Negotiation Status: not supported (0x0)
  Transmitted Modified TS Data 1: 0x0
    |--> Transmitted Modified TS Usage Mode: PCIe (0x0)
    |--> Transmitted Modified TS Information 1: 0x0
    |--> Transmitted Modified TS Vendor ID: 0x0
  Transmitted Modified TS Data 2: 0x0
    |--> Transmitted Modified TS Information 2: 0x0
    |--> Alternate Protocol Negotiation Status: not supported (0x0)
  Lane 0 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 1 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 2 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 3 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 4 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 5 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 6 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 7 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 8 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 9 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 10 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 11 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 12 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 13 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 14 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
  Lane 15 EQ Control: 0xf0
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x0
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0xf
$ ./pcieadm show-cfgspace -f ~/pci/00-05-01.pci pl32g
Physical Layer 32.0 GT/s Capability (0x2a)
  Capability Header: 0x5301002a
    |--> Capability ID: 0x2a
    |--> Capability Version: 0x1
    |--> Next Capability Offset: 0x530
  32.0 GT/s Capabilities: 0x501
    |--> Equalization Bypass to Highest NRZ Rate: supported (0x1)
    |--> No Equalization Needed: unsupported (0x0)
    |--> Modified TS Usage Mode 0 - PCI Express: supported (0x100)
    |--> Modified TS Usage Mode 1 - Training Set Message: unsupported (0x0)
    |--> Modified TS Usage Mode 2 - Alternate Protocol: supported (0x400)
  32.0 GT/s Control: 0x0
    |--> Equalization Bypass to Highest NRZ Rate: enabled (0x0)
    |--> No Equalization Needed: enabled (0x0)
    |--> Modified TS Usage Mode Selected: PCIe (0x0)
  32.0 GT/s Status: 0x0
    |--> Equalization 32.0 GT/s Complete: incomplete (0x0)
    |--> Equalization 32.0 GT/s Phase 1: unsuccessful (0x0)
    |--> Equalization 32.0 GT/s Phase 2: unsuccessful (0x0)
    |--> Equalization 32.0 GT/s Phase 3: unsuccessful (0x0)
    |--> Link Equalization Request 32.0 GT/s: 0x0
    |--> Modified TS Received: no (0x0)
    |--> Received Enhanced Link Behavior Control: full equalization required (0x0)
    |--> Transmitter Precoding: disabled (0x0)
    |--> Transmitter Precoding Request: disabled (0x0)
    |--> No Equalization Needed Received: no (0x0)
  Received Modified TS Data 1: 0x0
    |--> Modified TS Usage Mode Selected: PCIe (0x0)
    |--> Received Modified TS Information 1: 0x0
    |--> Received Modified TS Vendor ID: 0x0
  Received Modified TS Data 2: 0x0
    |--> Received Modified TS Information 2: 0x0
    |--> Alternate Protocol Negotiation Status: not supported (0x0)
  Transmitted Modified TS Data 1: 0x0
    |--> Transmitted Modified TS Usage Mode: PCIe (0x0)
    |--> Transmitted Modified TS Information 1: 0x0
    |--> Transmitted Modified TS Vendor ID: 0x0
  Transmitted Modified TS Data 2: 0x0
    |--> Transmitted Modified TS Information 2: 0x0
    |--> Alternate Protocol Negotiation Status: not supported (0x0)
  Lane 0 EQ Control: 0x47
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x7
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0x4
  Lane 1 EQ Control: 0x47
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x7
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0x4
  Lane 2 EQ Control: 0x47
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x7
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0x4
  Lane 3 EQ Control: 0x47
    |--> Downstream Port 32.0 GT/s Transmitter Preset: 0x7
    |--> Upstream Port 32.0 GT/s Transmitter Preset: 0x4
Actions #1

Updated by Electric Monk about 2 months ago

  • Gerrit CR set to 2295
Actions #2

Updated by Robert Mustacchi about 2 months ago

  • Description updated (diff)
Actions #3

Updated by Electric Monk about 2 months ago

  • Status changed from New to Closed
  • % Done changed from 0 to 100

git commit c3e0a1890221a18da85f545ad88e4933ca296566

commit  c3e0a1890221a18da85f545ad88e4933ca296566
Author: Robert Mustacchi <rm@fingolfin.org>
Date:   2022-08-16T18:20:40.000Z

    14893 pcieadm 32.0 GT/s physical layer capability decoding
    14894 pcieadm NPEM capability decoding
    Reviewed by: Benjamin Naecker <bnaecker@fastmail.com>
    Approved by: Patrick Mooney <pmooney@pfmooney.com>

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