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Bug #14947

open

PCIe bridge with only PF memory ends up with MAE unset

Added by Andy Fiddaman 3 months ago.

Status:
In Progress
Priority:
Normal
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Category:
-
Start date:
Due date:
% Done:

0%

Estimated time:
Difficulty:
Medium
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External Bug:

Description

If a PCIe device under a bridge has only prefetchable (PF) BARs then its parent bridge ends up having the Memory Access Enable (MAE) bit unset in its control register and then doesn't decode or forward any memory transactions.

Here's an example from a system with such a device.

First, the PCIe device.

# /usr/lib/pci/pcieadm show-cfgspace -d c9/0/0 \
    header0.command.mem header0.bar0 header0.bar2 header0.bar4
Device c9/0/0 -- Type 0 Header
  Command: 0x46
    |--> Memory Space: enabled (0x2)
  Base Address Register 0
    |--> Space: Memory Space (0x0)
    |--> Address: 0x101a0000000
    |--> Address: 64-bit (0x2)
    |--> Prefetchable: yes (0x1)
  Base Address Register 2
    |--> Space: Memory Space (0x0)
    |--> Address: 0x101a8000000
    |--> Address: 64-bit (0x2)
    |--> Prefetchable: yes (0x1)
  Base Address Register 4
    |--> Space: Memory Space (0x0)
    |--> Address: 0x101a8004000
    |--> Address: 64-bit (0x2)
    |--> Prefetchable: yes (0x1)

and then its parent bridge:

# /usr/lib/pci/pcieadm show-cfgspace -d c0/3/2 \
    header1.command.mem header1.secbus \
    header1.membase header1.pfbase header1.pfbasehi 
Device c0/3/2 -- Type 1 Header
  Secondary Bus Number: 0xc9
  Command: 0x45
    |--> Memory Space: disabled (0x0)               <-----------
  Memory Base: 0x0
    |--> Base: 0x0
  Prefetchable Memory Base: 0xa001
    |--> Addressing Capability: 64-bit (0x1)
    |--> Base: 0xa0000000
  Prefetchable Base Upper 32 bits: 0x101

This is because pcie_check_io_mem_range() in pcie only checks the non-PF memory base when deciding if there is any memory under the bridge, and that is zero here.

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