AMD family 0x15 PG support
In AMD family 0x15 processors cores come in pairs called compute units, sharing an FPU and L2 and L1I caches. This topology information needs to be detected and implemented as a Processor Group (PG).
Updated by Hans Rosenfeld over 9 years ago
- % Done changed from 0 to 80
Preliminary webrev: http://grumpf.hope-2000.org/illumos-2650-webrev/
Introduces cpi_compunitid, cpi_cores_per_compunit to struct cpuid_info, which are set according to the CPUID information. On systems not having compute units, cpi_compunitid is the same as cpi_coreid, while cpi_cores_per_compunit is 1.
A platform override for PGHW_FPU policy is added to account for the fact that L2 and L1I caches are shared, too, so it should include CMT_AFFINITY. I'm not sure that is really necessary, as I wasn't able to find any usage of CMT_AFFINITY in the code that would actually affect scheduling decisions.
Updated by Hans Rosenfeld about 9 years ago
- % Done changed from 80 to 100
Updated webrev: http://grumpf.hope-2000.org/illumos-2650-webrev-2/Changes:
- minor stylistic nits (L1I -> I$)
- Bugfix: Forgot to set chipid on family 0x15, causing all kinds of interesting panics on big systems. Reworked chipid setting to set chipid based on procnodeid and procnodes_per_pkg on all CPU families.
- Bugfix: The specification didn't tell whether the compute unit id in the CPUID data was system-wide just like the node id. It turns out it isn't, so work around it.
- 4-core family 0x10
- 8-core family 0x15 (1 node in 1 socket)
- 32-core family 0x15 (4 nodes in 2 sockets)
Updated by Albert Lee about 9 years ago
- Status changed from In Progress to Resolved
- Tags changed from needs-triage to amd
user: Hans Rosenfeld <email@example.com>
date: Thu May 03 15:56:05 2012 +0200
files: usr/src/uts/i86pc/os/cpuid.c usr/src/uts/i86pc/os/mp_machdep.c usr/
2650 AMD family 0x15 PG support
Reviewed by: Robert Mustacchi <firstname.lastname@example.org>
Reviewed by: Richard Lowe <email@example.com>
Approved by: Albert Lee <firstname.lastname@example.org>