Bug #4679
closed
want workaround for Intel erratum BT81
100%
Description
Intel erratum BT81, as follows:
TSC is Not Affected by Warm Reset
The TSC (Time Stamp Counter MSR 10H) should be cleared on reset. Due to this erratum the TSC is not affected by warm reset.
The TSC is not cleared by a warm reset. The TSC is cleared by power-on reset as expected. Intel has not observed any functional failures due to this erratum.
While gethrtime() is documented only to return the time since some arbitrary epoch, it would be nice if that epoch matched boot (like other x86 machines) instead of power-on (as it does given this erratum). While Intel documents no workaround, it seems like this should be as simple as clearing TSC on each CPU when it boots. Since not all CPUs boot at the same time, this may cause skew, but that can (and does) happen anyway, and existing code already handles it correctly.
Updated by Electric Monk over 8 years ago
git commit 4948216cdd0ccee7b9a4fd433ccab571afbb99e9
Author: Keith M Wesolowski <wesolows@foobazco.org> 4679 want workaround for Intel erratum BT81 Reviewed by: Robert Mustacchi <rm@joyent.com> Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com> Reviewed by: Dan McDonald <danmcd@omniti.com> Approved by: Dan McDonald <danmcd@omniti.com>
Updated by Robert Mustacchi over 8 years ago
- Status changed from New to Resolved
- % Done changed from 0 to 100