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- Registered on: 2011-07-27
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- illumos gate (Manager, Committer, 2011-08-10)
Reported issues: 584
- 05:00 PM illumos gate Feature #7865: Allow i40e to use multiple rings
- Hmm, if MAC was allowing the ring processing thread at the same time as the interrupt thread, that would explain a go...
- 06:45 PM illumos gate Bug #7828 (New): sysenter and sysexit dis should be allowed in 64-bit x86
- The sysenter and sysexit instructions are currently restricted to being disassembled as valid only in 32-bit x86 mode...
- 06:45 PM illumos gate Feature #7827 (New): dis tests for f16c, movbe, cpuid, msr, tsc, fence instrs
- This covers adding libdis tests for many smaller sets of instructions based on their cpuid bits.
- 06:44 PM illumos gate Bug #7826 (New): PCLMULQDQ psuedo-ops aren't properly described in dis
- The PCLMULQDQ instructions has a couple variants or psuedo-ops that end up assembling to the same instruction. We sho...
- 06:43 PM illumos gate Feature #7825 (New): want avx dis tests
- It would be nice if the dis tests supported avx instructions.
- 01:12 AM illumos gate Feature #7791 (New): GLDv3 plumbing for 25GbE and 50GbE
- As we have devices which are starting to support 25 GbE and 50 GbE is on the way, we should flesh out the GLDv3 to fu...
- 01:12 AM illumos gate Feature #7790 (New): Want support for XXV710
- We should update the Intel common code and add support for the XXV710 parts. While this update also adds support for ...
- 07:58 PM illumos gate Feature #7758 (Closed): want SSE 4.1 disasm tests
- It'd be good to have disasm tests for the SSE 4.1 instruction set.
- 07:58 PM illumos gate Feature #7757 (Closed): want avx2 disasm tests
- It'd be good to have disasm tests for the AVX2 instructions.
- 07:57 PM illumos gate Bug #7756 (Closed): dis can't handle x86 SSE 3 instructions
Intel added several instructions to SSE 3 which dis can't handle. These include:
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